CMOS Transistor Theory (and its effects on scaling) Michael Niemier - PowerPoint PPT Presentation

CMOS Transistor Theory (and its effects on scaling) Michael Niemier (Some slides based on lecture notes by David Harris)

Nanowire-based Gates Can make very small pn junctions and diode based lgoic If each wire was just 5 nm in diameter, would you be excited about this technology?

MOSFET cross section… With applied V gs , depletion region forms n n P

To recap… • So far, we have treated transistors as ideal switches • An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships • Transistor gate, source, drain all have capacitance – I = C ( Δ V/ Δ t) -> Δ t = (C/I) Δ V – Capacitance and current determine speed

MOS Capacitor • Gate and body form MOS capacitor • Operating modes polysilicon gate V g < 0 silicon dioxide insulator + p-type body - (a) 0 < V g < V t depletion region + - (b) V g > V t inversion region + depletion region - (c)

Terminal Voltages • Mode of operation depends on V g , V d , V s – V gs = V g – V s – V gd = V g – V d – V ds = V d – V s = V gs - V gd • Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence V ds ≥ 0 • nMOS body is grounded. First assume source is 0 too. • Three regions of operation – Cutoff V g – Linear + – Saturation + V gs V gd - - V s V d - V ds +

nMOS Cutoff • No channel formed, so no current flows • I ds = 0 V gs = 0 V gd + g + - - s d n+ n+ p-type body b

nMOS Linear • Channel forms V gs > V t V gd = V gs + g + • Current flows from d to s - - s d – e - from s to d V ds = 0 n+ n+ • I ds increases with V ds p-type body b • Similar to linear resistor V gs > V t V ds = 0, no current V gs > V t V gs > V gd > V t g + + - - d I ds s n+ n+ 0 < V ds < V gs -V t p-type body b V gs > V t V ds > 0, but < (V gs - V t ) (current flows)

nMOS Saturation • Channel pinches off • I ds independent of V ds • We say current saturates • Similar to current source V gs > V t V gd < V t g + + - - d I ds s n+ n+ V ds > V gs -V t p-type body b V ds > V gs - V t Essentially, voltage difference over induced channel fixed at V gs - V (current flows, but saturates) (or i ds no longer a function of V ds )

Outline (part 2) • Today… – nMOS & pMOS I-V characteristics • Why (part 1): – Quantify - or at least estimate - how we represent & move information • Why (part 2): – This way we can estimate what happens when we make device smaller -- and in theory, better. • Possibly today… – A very brief discussion of RC delay models • Why? – Important because delay = one of the 2 performance metrics we care most about. • Another, “why” – Can leverage in 1st HW :-) • David Frank talk - starts with 1st principles, extrapolates to practical, chip-level performance

A little bit of foreshadowing Parameter Relation Full Scaling General Scaling Fixed-Voltage Scaling W, L, t ox 1/S 1/S 1/S V dd , V t 1/S 1/U 1 N SUB V/W depl S S 2 /U S 2 2 Area/device WL 1/S 2 1/S 2 1/S 2 C ox 1/t ox S S S C gate C ox WL 1/S 1/S 1/S k n , k p C ox W/L S S S I sat C ox WV 1/S 1/U 1 I sat /Area S S 2 /U S 2 Current Density R on V/I sat 1 1 1 R on C gate 1/S 1/S 1/S Intrinsic Delay P I sat V 1/S 2 1/U 2 1 P/Area 1 S 2/ U 2 S 2 Power Density  Board digression # 0

A little bit of foreshadowing  Board digression # 0

A little bit of foreshadowing  Board digression # 0

t ox 350 nm 8/6~1.333 350/250=1.4 250 nm 6/3.8~1.58 250/180~1.39 180 nm 3.8/2.6~1.46 180/150~1.2 150 nm 2.6/1.5~1.7 150/120~1.25 1.5/1.2~1.25 120 nm 90 nm 1.25/1~1.25 120/90~1.33 65 nm 90/65~1.38

Ok, let’s derive some I-V relationships

I-V Characteristics • In Linear region, I ds depends on – How much charge is in the channel? – How fast is the charge moving?

Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Q channel = gate V g + + polysilicon V gs C g V gd gate source drain W - - V s V d channel t ox - + n+ n+ V ds SiO 2 gate oxide L n+ n+ (good insulator, � ox = 3.9) p-type body p-type body  Board digression # 1

Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Q channel = CV • C = gate V g + + polysilicon V gs C g V gd gate source drain W - - V s V d channel t ox - + n+ n+ V ds SiO 2 gate oxide L n+ n+ (good insulator, � ox = 3.9) p-type body p-type body

Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Q channel = CV • C = C g = ε ox WL/t ox = C ox WL • V = C ox = ε ox / t ox gate V g + + polysilicon V gs C g V gd gate source drain W - - V s V d channel t ox - + n+ n+ V ds SiO 2 gate oxide L n+ n+ (good insulator, � ox = 3.9) p-type body p-type body

Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Q channel = CV • C = C g = ε ox WL/t ox = C ox WL • V = V gc – V t = (V gs – V ds /2) – V t C ox = ε ox / t ox gate V g + + polysilicon V gs C g V gd gate source drain W - - V s V d channel t ox - + n+ n+ V ds SiO 2 gate oxide L n+ n+ (good insulator, � ox = 3.9) p-type body p-type body  Board digression # 2

Carrier velocity • Charge is carried by e- • Carrier velocity v proportional to lateral E-field between source and drain • v =

Carrier velocity • Charge is carried by e- • Carrier velocity v proportional to lateral E-field between source and drain • v = µ E µ called mobility • E = How I try not to teach…  Board digression # 3

Carrier velocity • Charge is carried by e- • Carrier velocity v proportional to lateral E-field between source and drain • v = µ E µ called mobility • E = V ds /L • Time for carrier to cross channel: – t =

Carrier velocity • Charge is carried by e- • Carrier velocity v proportional to lateral E-field between source and drain • v = µ E µ called mobility • E = V ds /L • Time for carrier to cross channel: – t = L / v  Board digression # 4

nMOS Linear I-V • Now we know – How much charge Q channel is in the channel – How much time t each carrier takes to cross I = ds

nMOS Linear I-V • Now we know – How much charge Q channel is in the channel – How much time t each carrier takes to cross Q I channel = ds t =

nMOS Linear I-V • Now we know – How much charge Q channel is in the channel – How much time t each carrier takes to cross Q I channel = ds t W V � � C V V V ds = µ � � � � 2 ox gs t ds L � � W V � � = C V V V � µ ds = � � � � � ox 2 L gs t ds � �  Board digression # 5

Let’s go back to… Parameter Relation Full Scaling General Scaling Fixed-Voltage Scaling W, L, t ox 1/S 1/S 1/S V dd , V t 1/S 1/U 1 N SUB V/W depl S S 2 /U S 2 2 Area/device WL 1/S 2 1/S 2 1/S 2 C ox 1/t ox S S S C gate C ox WL 1/S 1/S 1/S k n , k p C ox W/L S S S I sat C ox WV 1/S 1/U 1 I sat /Area S S 2 /U S 2 Current Density R on V/I sat 1 1 1 R on C gate 1/S 1/S 1/S Intrinsic Delay P I sat V 1/S 2 1/U 2 1 P/Area 1 S 2/ U 2 S 2 Power Density  Board digression # 6

nMOS Saturation I-V • If V gd < V t , channel pinches off near drain – When V ds > V dsat = V gs – V t • Now drain voltage no longer increases current I = ds

nMOS Saturation I-V • If V gd < V t , channel pinches off near drain – When V ds > V dsat = V gs – V t • Now drain voltage no longer increases current V � � � I V V V dsat = � � � � 2 ds gs t dsat � �

nMOS Saturation I-V • If V gd < V t , channel pinches off near drain – When V ds > V dsat = V gs – V t • Now drain voltage no longer increases current V � � I V V V dsat = � � � � � 2 ds gs t dsat � � � 2 ( ) V V = � gs t 2  Board digression # 7

nMOS I-V Summary • Shockley 1 st order transistor models � 0 V V cutoff � < gs t � V � � � I V V V V V linear ds = � � � < � � � 2 ds gs t ds ds dsat � � � � � 2 ( ) V V V V saturatio n � > � gs t ds dsat 2 �

Again, let’s go back to… Parameter Relation Full Scaling General Scaling Fixed-Voltage Scaling W, L, t ox 1/S 1/S 1/S V dd , V t 1/S 1/U 1 N SUB V/W depl S S 2 /U S 2 2 Area/device WL 1/S 2 1/S 2 1/S 2 C ox 1/t ox S S S C gate C ox WL 1/S 1/S 1/S k n , k p C ox W/L S S S I sat C ox WV 1/S 1/U 1 I sat /Area S S 2 /U S 2 Current Density R on V/I sat 1 1 1 R on C gate 1/S 1/S 1/S Intrinsic Delay P I sat V 1/S 2 1/U 2 1 P/Area 1 S 2/ U 2 S 2 Power Density  Board digression # 8

Look at I DS in context of scaling  Board digression # 8

 Board digression # 8