Transistor-Level Gate Modeling for Nano Transistor-Level Gate - PowerPoint PPT Presentation

Transistor-Level Gate Modeling for Nano Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering CMOS Circuit Verification Considering Statistical Process Variations Statistical Process Variations Qin Tang Amir Zjajo Michel Berkelaar Nick van der Meijs Contact: Q.tang@tudelft.nl Sept. 10, PATMOS 2010

Outline Motivations Motivations Statistical Simplified Transistor Model RDE-based statistical simulator Results Conclusion 1

Cell modeling for circuit verification Gate-level modeling unique model for timing, noise and power droop analysis STA: Delay / S out ------ f(S in , C eff )  Nonlinear resistive Load: a single linear capacitance value  Input signal : slew  Current source model  unified model for timing, noise and power droop analysis is feasible 2

Basic current source model S in & C eff No internal based charge effects V out C eff C cell I cell C eff ramp Single Switching Assumption (fail for multi-input switching MIS ) 3

Optimization of GLM I cell , C cell ---- f( V in ,V out ) MIS ? method1 for MIS Delay & S out ---- f(V in1 ,V in2 ,…,V out1 ,V out2 …) 4

Optimization2 PI1 PO1 Internal Port PI2 PO2 . . . . . . . . . . . . . . . PIN PON Trend: complexity ↑↑↑ Root: black-box property of gate-level model 5

Our solution for modeling  independent of input waveform and output load  able to capture MIS and internal charge effects  device-level accuracy  easy to characterize has statistical extension for SSTA  Transistor-level Gate Modeling 6

Outline Motivations Statistical Simplified transistor model Statistical Simplified Transistor Model RDE-based statistical simulator Results Conclusion 7

SSTM structure SSTM: statistical simplified transistor model ξ p : process variation STM: no process variations 8

Nominal I-V model Drain current BSIM4-based   V V W    dseff  dseff     I JV V V V   (1 ) (1 ) [1 ( )] d s gst dseff ds dseff 0 L V V   2 b c          V V V K V K V ( ) th th ds s bs s bs 0 1 2 Simplification  V th — no consideration for narrow channel effect & linear dependence of V th on V ds  J — mobility degradation  λ — channel length modulation, drain induced barrier lowering ( DIBL ) and substrate induced body effect . 9

Nominal C-V model Conventional modeling Accuracy: analytical method    C Q V / ij i j Fast computation: single value Our modeling  constant value in cutoff gate channel capacitances and saturation regions; ( C gs , C gd , C gb ):  Linear function in linear region Junction depletion capacitances single value ( C sb , C db ): 10

Statistical extension m        I t I t t ( , ) ( ) ( ) ds ds k k 0  k 1 m        C t C t t ( , ) ( ) ( ) j j k k 0  k 1    p p p : random parameter vector 0  : parameter variation from the nominal value p 0 C : nominal value of the j th capacitance j 0   , : sensitivities to the random parameters 11

Outline Motivations Statistical Simplified Transistor Model RDE-based statistical simulation RDE-based statistical simulator Results Conclusion 12

Random Modified Nodal Analysis (MNA) General analysis flow   F x x t p x t x ' ( , , , ) 0 ( )     F x x t p 0 x t 0 x 0 ' ( , , , ) 0 ( ) x DC: initial vector 0 0 0 Random MNA Tran.: solution x s Numerical integration methods ( e.g. Backward Euler, Trapezoidal ) Newton-Raphson-like method 13

Solving random MNA system Linearization            F x x t p F x x t p C x x A t x x B t ' ' ' ' ( , , , ) ( , , , ) ( ) ( ) ( ) ( ) 0 s s s s 0 1 st -order Taylor expansion at ( x s ’, x s , p 0 ) Reorganization     y x x x t y t x t ( ) ( ) ( ) s s      y t E t y t F t y t Random Differential Equation ' ( ) ( ) ( ) ( ) ( ) x 0 0 (RDE) Solution ( m. s. integral theorem)     y t t Assume the initial ( ) ( ) condition is deterministic        t E t t F t t ' ( ) ( ) ( ) ( ) ( ) 0 ODE 0 14

Statistical output    E x t x t ( ) ( ) s m     '     Var x t t Var 2 ( ) ( ) j jk k  k 1                   T Cov x x t diag Var Var t ( , ) , ,   i i i m i 1 1 ' 1 Analysis output is time-index voltage array for STA, and time-index mean, variance and covariance array for SSTA Only need to simulate once, no need to sample random parameters and then simulate thousands of times. No assumption for the distribution of random process variables 15

Probability density function ( pdf ) V (t- Δ t) V (t) V η V η V (t) V (t- Δ t)       t t V t t V V t V ฀ rising Pr( ) Pr( ( ) ( ) )    r o o         V t t V V t t V V t V ฀ ฀ Pr( ( ) ) Pr( ( ) ( ) )    o o o       t t V t t V V t V falling ฀ Pr( ) Pr( ( ) ( ) )    f o o        V t V V t t V V t V ฀ Pr( ( ) ) Pr( ( ) ( ) )    o o o 16

Outline Motivations Statistical Simplified Transistor Model RDE-based statistical simulator Results Results Conclusion 17

STM (nominal SSTM) Relative error of delay ( % ) Output slew 9 8 SSTM results 2 BSIM4 results scaled output rising slew 7 1 Relative Error (%) 6 0 -1 5 -2 4 -3 3 -4 2 0.5 30 0.4 25 0.3 20 1 0.2 15 10 0.1 5 0 0 0 0 5 10 15 20 25 Slew (ns) C load (fF) C load (fF) 18

STM for MIS Results of a NAND2 with simultaneous MIS 1 0.8 Voltage (V) 0.6 0.4 2 Vins Vout_ BSIM4 0.2 Vout_ STM 0 0 0.5 1 1.5 2 2.5 3 Able to time (ns) capture MIS scenario 19

Power grid analysis Essential: large current drawn through resistive power supply network Requirement: simulating dynamic current drawn through VDD pins 0.5 0 -0.5 t n SSTM result rre Spectre result -1 u c d le -1.5 a c s -2 -2.5 -3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 scaled time current drawn by a cell from the power grid 20

Signal integrity verification Aggressor …… .. V_in Cross- cap Active …… .. load V_noise driver 1 noisy input voltage (V) aggressor 0.8 SSTM output Spectre output 0.6 0.4 0.2 0 0 0.5 1 1.5 scaled time 21

Statistical evaluation Average 40 × speedup Comparison of μ , σ , and CPU time of delay between Spectre and RDE-based method μ (10 -9 ) Standard σ (10 -11 ) CPU time (s) cells Spectre RDE err(%) Spectre RDE err(%) Spectre RDE INV_X1 0.3777 0.3779 0.00% 3.3407 3.4753 4.03% 91 1.35 INV_X2 0.1986 0.1998 0.60% 1.6113 1.7140 6.37% 91 1.35 INV_X4 0.1148 0.1135 1.10% 0.7103 0.7308 3.96% 91 1.35 BUF_X1 0.3914 0.3915 0.00% 3.7228 3.5644 4.25% 200 5.9 BUF_X2 0.2215 0.2217 0.01% 1.4150 1.5100 7.10% 200 6.0 BUF_X4 0.1554 0.1535 1.20% 0.9995 1.0481 4.80% 200 6.0 NAND_X1 0.3830 0.3842 0.31% 3.4579 3.5618 3.01% 197 6.6 NAND_X2 0.2063 0.2080 0.82% 1.7487 1.7843 2.03% 197 6.6 NOR_X1 0.5040 0.4974 1.31% 4.4148 4.2930 2.70% 198 10 NOR_X2 0.2635 0.2598 1.40% 2.2557 2.1389 5.18% 198 10 Matlab Vs 1000 × MC in Spectre 22

Outline Motivations Statistical Simplified transistor model RDE-based statistical simulator Results Summary Conclusion 23

Conclusion Transistor-level gate modeling  independent of input waveform and output load; able to capture MIS and internal charge effects; easy to characterize and quite accurate, etc.  comprehensively handles electrical issues traditionally problematic for static timing analysis. Statistical Simplified Transistor Model (SSTM)  Nominal Ids model: BSIM4-based  Single value -- Nominal cap model -- analytical model  Statistical extension: linear Taylor expansion  Able to handle accuracy limitations of traditional cell models.  Possible to handle requirements of noise and power analysis  Compatible with RDE-based simulator for statistical timing analysis 24

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