Quo Vad adis? = = Wher ere e are e you going? 2 I I I -V - PowerPoint PPT Presentation

I I I -V CMOS: Quo Vad adis? J. A. del Alamo, X. Cai, W. Lu, A. Vardi, and X. Zhao Microsystems Technology Laboratories Massachusetts Institute of Technology Compound Semiconductor Week 2018 Cambridge, MA, May 29-June 1, 2018 Acknowledgements: • Former students and collaborators: D. Antoniadis, E. Fitzgerald, J. Grajal, J. Lin • Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung, SRC • Labs at MIT: MTL, EBL

Quo Vad adis? = = Wher ere e are e you going? 2

I I I -V CMOS: The Promise Scaling: Voltage ↓  Current density ↓  Performance ↓ Current density of n-MOSFETs Source injection velocity: Si vs. at nominal voltage: InGaAs FETs del Alamo, Nature 2011 v inj (InGaAs) > 2v inj (Si) at less than half V DD  high current at low voltage 3

Transconductance of Planar Si vs. I nGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage “Comparisons always fraught with danger…” 4

Transconductance of Planar Si vs. I nGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage “Comparisons always fraught with danger…” • InGaAs stagnant for a long time 5

Transconductance of Planar Si vs. I nGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage “Comparisons always fraught with danger…” • Rapid recent progress • InGaAs exceeds Si 6

Transconductance of Planar Si vs. I nGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage “Comparisons always fraught with danger…” MIT (V DS =0.5 V) • Rapid recent progress Lin, IEDM 2014 • InGaAs exceeds Si EDL 2016 7

Many requirements for a successful logic technology 1. ON current 2. OFF current 3. Scalability 4. Stability 5. Manufacturing robustness 6. Si integration 8

Evolution of transistor structure for improved scalability Planar bulk Nanowire MOSFET MOSFET Thin-body SOI MOSFET FinFET Enhanced gate control  improved scalability 9

Evolution of transistor structure for improved scalability FinFET Enhanced gate control  improved scalability 10

Transconductance of planar Si vs. I nGaAs MOSFETs 11

Transconductance of Si vs. I nGaAs FinFETs 12

Transconductance of Si vs. I nGaAs FinFETs W f g m normalized by fin width FinFET: large increase in current density per unit footprint over planar MOSFET 13

Transconductance of Si vs. I nGaAs FinFETs W f MIT (V DS =0.5 V) g m normalized by fin width Best InGaAs FinFETs nearly match 14 nm Si MOSFETs 14

Transconductance of Si vs. I nGaAs FinFETs 10 nm node Intel (V DS =0.7 V) W f g m normalized by fin width 10 nm node Si MOSFETs a great new challenge! 15

I nGaAs FinFETs @ MI T Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Vardi, • Sub-10 nm fin width DRC 2014, • Aspect ratio > 20 EDL 2015, • Vertical sidewalls IEDM 2015 16

I nGaAs FinFETs @ MI T Mo Mo High-K HSQ SiO 2 HSQ L g W/Mo High-K n + -InGaAs InP InGaAs InGaAs δ - Si InAlAs InP Vardi, IEDM 2017 • Si-compatible process • Contact-first, gate-last process • Fin etch mask left in place  double-gate MOSFET 17

Most aggressively scaled FinFET W f =5 nm, L g =50 nm, H c =50 nm (AR=10), EOT=0.8 nm: 1E-3 L g =50 nm V DS =500 mV V GS =-0.2 to 0.5 V W f =5 nm 1E-4 150 ∆ V GS =0.1 V 50 mV 1E-5 I d [A/ µ m] 100 I d [ µ A/ µ m] 1E-6 S sat =75 mV/dec S lin =65 mV/dec 1E-7 50 1E-8 1E-9 -0.2 0.0 0.2 0.4 0.6 0.8 0 V GS [V] 0.0 0.1 0.2 0.3 0.4 0.5 700 V DS =0.5 V g m,max =565 µS/µm V GS [V] Normalized by 600 L g =50 nm conducting gate 500 W f =5 nm At V DS =0.5 V: g m [ µ S/ µ m] periphery = 2H c 400 • g m =565 µS/µm 300 200 R on =660 Ω .µm • 100 • S sat =75 mV/dec 0 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 • DIBL=22 mV/V Vardi, IEDM 2017 V GS [V] 18

Fin-width scaling of ON-state current 2.0 Vardi, IEDM 2017 1.5 g m [mS/ µ m] in planar 1.0 MOSFETs expect L g =40-60 nm 2.2 mS/µm 0.5 V DS = 0.5 V 0.0 0 5 10 15 20 25 W f [nm] Normalized by conducting 1000 gate periphery = 2H c 800 • g m independent of W f down R on [ Ω - µ m] 600 to W f =7 nm • In planar MOSFET (x=0.53) 400 expect g m ~ 2.2 mS/µm 200 • Missing performance hints 0 0 5 10 15 20 25 at sidewall damage W f [nm] 19

Fin-width scaling of OFF-state current S sat (V DS = 0.5 V) 120 S sat 1E-3 L g =50 nm V DS =500 mV S lin W f =5 nm 1E-4 50 mV 100 1E-5 S [mV/dec] I d [A/ µ m] 80 1E-6 S sat =75 mV/dec S lin (V DS = 50 mV) S lin =65 mV/dec 1E-7 60 1E-8 L g =40-60 nm 1E-9 -0.2 0.0 0.2 0.4 0.6 0.8 40 0 5 10 15 20 25 V GS [V] W f [nm] • Excellent subthreshold swing scaling behavior • From long L g devices: D it ~ 8x10 11 cm -2 .eV -1 Vardi, IEDM 2017 20

Excess OFF-state current Band-to-band tunneling (BTBT) at drain end of channel Zhao, EDL 2018 Classic BTBT behavior in long-channel devices 21

Excess OFF-state current Current multiplication through parasitic bipolar transistor -1 slope • Large BJT current gain (up to ~100) Short L g : β ~ 1/L g • Long L g : β ~ exp(-L g /L d ), L d ≈ 2 -4 µm • Zhao, EDL 2018, CSW 2018 22

Manufacturing robustness: impact of fin width on V T InGaAs doped-channel FinFETs: 50 nm thick, N D ~10 18 cm -3 Vardi, IEDM 2015 T=90K • Strong V T sensitivity for W f < 10 nm; much worse than Si • Due to quantum effects • Big concern for future manufacturing 23

MOSFET threshold voltage stability Planar InGaAs MOSFETs under forward-gate stress (V gs >0): 2.5 nm HfO 2 • ∆ V t : power law in time and stress voltage • Typical of PBTI (Positive Bias Stress Instability) Cai, IEDM 2016 24

MOSFET stability due to oxide traps Planar InGaAs MOSFETs under forward-gate stress: 9 V gt =0.4 V 10 time to 30mV shift (s) @ 10 years 7 10 5 10 3 10 1 10 0.4 0.6 0.8 1 1.2 V gt,stress (V) • ∆ g m,max and ∆ V t,lin correlated • Negligible change in S • 30 mV shift in 10 years for V gt = 0.4 V • Oxide traps = O vacancies in HfO 2 Excellent review by Franco, IEDM 2017 Cai, IEDM 2016 25

Other manifestations of oxide traps C-V frequency dispersion g m frequency dispersion Pulsed vs. DC Cai, CSW 2018 Also: Johansson, ESSDERC 2013 • Frequency dispersion in C g and g m Pulsed I- V ≠ DC I -V • • DC underestimates transistor potential Also: Cartier, ESSDERC 2017 26

I nGaAs Vertical Nanowire MOSFETs VNW MOSFET Vertical NW MOSFET:  uncouples footprint scaling from L g , L spacer , and L c scaling 27

I nGaAs VNW-MOSFETs by top-down approach @ MI T Lu, EDL 2017 • Top-down approach: flexible and manufacturable • Critical technologies: precision RIE + alcohol-based digital etch 28

D= 7 nm I nGaAs VNW MOSFET -3 V ds =0.5 V 10 800 V gs = 0 V to 0.8 V in 0.1 V step D = 7 nm -4 700 10 D = 7 nm Top contact = Drain 600 -5 10 V ds =0.05 V I d ( A/ µ m ) I d (µ A/ µ m) 500 -6 10 400 -7 10 300 S lin /S sat = 85/90 mV/dec -8 10 DIBL = 222 mV/dec 200 100 -9 10 -0.2 0.0 0.2 0.4 0.6 0 0.0 0.1 0.2 0.3 0.4 0.5 V gs (V) V ds (V) 100 V gs = 0 V to 0.8 V in 0.1 V step Single nanowire MOSFET: D = 7 nm 80 Top contact = Source • L ch = 80 nm I d (µ A/ µ m) 60 • 2.5 nm Al 2 O 3 (EOT = 1.3 nm) 40 • g m,pk =1700 µS/µm 20 • Top contact = key problem 0 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) Zhao, IEDM 2017 29

Benchmark with Si/ Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs MIT @ V DS =0.5 V Zhao, IEDM 2017 • First sub-10 nm diameter VNW FET of any kind on any material system • InGaAs competitive with Si [hard to add strain] 30

I nGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Vapor-Solid-Liquid Selective-Area Epitaxy (SAE) (VLS) Technique Riel, MRS Bull 2014 VNW MOSFETs: path for III-V integration on Si for future CMOS Riel, IEDM 2012 31

Conclusions 1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Device performance still lacking for 3D architecture designs  severe oxide trapping masks true transistor potential 3. Serious challenges identified: excess off-current, stability, manufacturability, integration with Si 4. Vertical Nanowire MOSFET: ultimate scalable transistor; integrates well on Si 32