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ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 - PowerPoint PPT Presentation

May 27, 2023 •292 likes •608 views

ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste CMOS VLSI Design Global Foundries: BiCMOS_8HP8XP_Training.pdf BiCMOS_8HP_Design_Manual.pdf Physical design process overview CMOS transistor

  1. ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste – “CMOS VLSI Design” Global Foundries: “BiCMOS_8HP8XP_Training.pdf” “BiCMOS_8HP_Design_Manual.pdf”

  2. Physical design process overview  CMOS transistor structure and fabrication steps  Standard cell layouts  Creation, verification & characterization of a standard-cell based logic circuit block  Creation of a chip from circuit blocks 2 ELEC 5250/ 6250/ 6256

  3. ASIC layout 3 ELEC 5250/ 6250/ 6256

  4. ASIC Design Flow Behavioral Verify Design Function DFT/BIST Gate-Level Verify & ATPG Netlist Function Transistor-Level Verify Function Netlist & Timing DRC & LVS Physical Verify Verification Layout Timing Mask Data 4 ELEC 5250/ 6250/ 6256

  5. ASIC Design Flow 5 ELEC 5250/ 6250/ 6256

  6. IC “Floorplan” 6 ELEC 5250/ 6250/ 6256

  7. CMOS standard cell layout (generic) Source: Weste “CMOS VLSI Design” 7 ELEC 5250/ 6250/ 6256

  8. BiCMOS8HP NAND2_A Cell (LEF file) Yellow – “Pins” Orange = Poly Blue = Metal1 Cadence Encounter “Cell Viewer” Tool 8 ELEC 5250/ 6250/ 6256

  9. BiCMOS8HP DFFS_B Cell (LEF file) Yellow – “Pins” Orange = Poly Blue = Metal1 Cadence Encounter “Cell Viewer” Tool 9 ELEC 5250/ 6250/ 6256

  10. Standard Cell-Based Block 10 ELEC 5250/ 6250/ 6256

  11. Global Foundries BiCMOS8HP process cross-section “Passivation” 11 ELEC 5250/ 6250/ 6256

  12. BiCMOS8HP process cross-section External Connections Via Aluminum Via Via Copper Via PC = Polysilicon CA = Contact to diffusion/poly 12 ELEC 5250/ 6250/ 6256

  13. BiCMOS8HP metallization options: AM Analog Metal (RF wiring) 13 ELEC 5250/ 6250/ 6256

  14. Basic N-channel MOS transistor drain gate bulk + + + + V GS L V DS V GS source V DS W T ox gate bulk n -type n -type electrons source drain GND or depletion VSS E x region p -type mobile channel charge fixed depletion charge 14 ELEC 5250/ 6250/ 6256

  15. CMOS Inverter Cross-Section Source: Weste “CMOS VLSI Design” 15 ELEC 5250/ 6250/ 6256

  16. Inverter cross-section with well and substrate contacts Source: Weste “CMOS VLSI Design” 16 ELEC 5250/ 6250/ 6256

  17. IC fabrication process 2 4 1 hour 3 5 1 furnace wafer spin resist grow crystal saw grow oxide etch As + resist oxide mask 6 7 8 9 10 11 12 8. Etch exposed oxide 4. Grow oxide SiO2 9-10. Implant ions in exposed substrate 5. Apply photoresist 11. Strip resist 6. UV light exposes resist 12. Etch oxide 7. Remove exposed resist 17 ELEC 5250/ 6250/ 6256

  18. P-substrate CMOS SiO2 layer Process Photoresist steps Expose and etch Etch SiO2 Remove photoresist Implant n-well Remove SiO2 Source: Weste “CMOS VLSI Design” 18 ELEC 5250/ 6250/ 6256

  19. Deposit poly CMOS Process Etch steps Deposit SiO2 Etch Diffusion Remove SiO2 Source: Weste “CMOS VLSI Design” 19 ELEC 5250/ 6250/ 6256

  20. Inverter mask set N-well Generated by IC layout tools Poly N+ diffusion “Layout” is a set of patterns for P+ diffusion each layer. Contacts Metal Source: Weste “CMOS VLSI Design” 20 ELEC 5250/ 6250/ 6256

  21. Inverter mask set 21 ELEC 5250/ 6250/ 6256

  22. Standard Cell Mask Set (Submitted to foundry) Source: Smith, Figure 2.7 22 ELEC 5250/ 6250/ 6256

  23. MOSIS fabrication processes (www.mosis.org)  TSMC Fabrication Processes 28, 40, 65, 90, 130, 180 and 350 nanometer processes. Tiny2 program is also available on 65 and 180nm processes.  GlobalFoundries Fabrication Processes 14 nm, 28 nm, 40 nm, 55 nm, 0.13 µm,0.18 µm, 9HP (90 nm), 8HP (0. 13 µm), 8XP (0.13 µm), 7WL (0.18 µm), 7RF SOI (0.18 µm) 7SW (0. 18 µm) 9WG (90 nm), 9WG (90 nm), andTinyChip processes .  ON Semiconductor Fabrication Processes 0.7 µm high voltage CMOS, 0.5 µm CMOS, and 0.35 µm high voltage CMOS.  ams AG Fabrication Processes 180 and 350 nanometer processes - CMOS and high voltage CMOS and SiGe-BiCMOS .  AIM Fabrication Processes AIM Photonics Fabrication 23 ELEC 5250/ 6250/ 6256

  24. (Older) MOSIS fab processes (http://www.mosis.org) AMI bought by ON Semiconductor: http://www.onsemi.com/ TSMC (Taiwan Semiconductor): http://www.tsmc.com =ON =ON Scalable CMOS Mentor Graphics ASIC Design Kit Source: Weste “CMOS VLSI Design” 24 ELEC 5250/ 6250/ 6256

  25. Scalable CMOS process design rules 1. well 2. active 3. poly 1 2 3 3 (2.1) 10 (1.1) 5 (2.3) 3 (2.4) nwell 1 (3.5) nwell 3 0 or 4 pdiff (2.2) (2.5) nwell 3 (3.4) pdiff pdiff ndiff nwell 0 (1.4) 9 (1.2) 2 (3.3) ndiff ndiff pdiff 3 0 or 4 2 (3.2) hot (2.2) pwell (2.5) pwell 0 or 6 (1.3) poly 5 (2.3) 3 (2.4) 3 (2.1) pwell 2 (3.1) 4 4. select pwell nwell 5. poly 5 1.5 2 (5.3a) p-select n-select contact (5.2a) poly pdiff 2 2 (5.1a) ndiff 6. active 6 3 (4.1) 1 (4.3) contact nwell 2 (6.3a) poly 1.5 (6.2a) 2 (6.4a) ndiff pdiff 2 (4.2) n-select p-select poly 2 2 1.5 8. via1 7 7. metal1 8 (6.1a) (6.2a) 1 (7.3) pdiff poly 2 (8.4) 3 (7.1) 2 (8.5) poly via1 1 (8.3) 3 metal2 contact (7.2a) m1 m2 active m1 2 (8.5) poly 2 2 (8.1) contact 2 (7.2b) 3 (8.2) ndiff 1 (7.4) 10. overglass (micr 10 ons) 15. metal3 9 9. metal2 14 15 14. via2 30 (10.4) 6 (10.3) m3 3 (9.1) 2 2 (14.1) 2 (14.4) m3 6 m2 m2 1 (15.1) (14.3) m2 via2 via1 4 (15.2) m3 15 3 1 (10.5) 3 via1 glass (14.2) (9.3) via2 (9.2b) 4 (9.2a) m3 m1 m2 m1 100 100 (10.1) 2 (15.3) Source: Smith, Figure 2.11 25 ELEC 5250/ 6250/ 6256

  26. MOSIS Design Rules Smith text: Tables 2.7-2.9 26 ELEC 5250/ 6250/ 6256

  27. MOSIS Design Rules Smith text: Tables 2.7-2.9 27 ELEC 5250/ 6250/ 6256

  28. MOSIS Design Rules Smith text: Tables 2.7-2.9 28 ELEC 5250/ 6250/ 6256

  29. MOSIS Design Rules Smith text: Tables 2.7-2.9 29 ELEC 5250/ 6250/ 6256

  30. MOSIS Design Rules Smith text: Tables 2.7-2.9 30 ELEC 5250/ 6250/ 6256

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