Tota otal S Sens ensitivity B Bas ased ed DFM FM Optimiz mizat ation ion of of Standar ndard L d Library Cells lls Yongchan Ban, Savithri Sundareswaran*, and David Z. Pan ECE Dept., The University of Texas, Austin, TX *Freescale Semiconductor, Austin, TX TM 1
Outline line Motivation Our Contribution Total Sensitivity › Device criticality based sensitivity › Lithography proximity induced sensitivity › Process variation induced sensitivity Total Sensitivity Based Layout Optimization Experimental Results Conclusions 2
Current Lithography Challenges 10 [Courtesy Intel] -nce 1 um 0.1 [Courtesy Intel, 2006] 1980 1990 2000 2010 2020 Optical lithography (193nm) will continue for several years. › Immersion, RET (Resolution Enhancement Technique, e.g. OPC) › DPL (Double Patterning Lithography) Next Generation Lithography (e.g. EUV) › Economical/material/technical challenges 3
Gate Variation @ Standard Cell Active Corner Rounding Line-end Shortening Poly Corner Rounding Process Variation 4
Impact of Gate Length Variation Δ L gate is up to 10% @45nm node. 30 NMOS 2 NMOS Leakage 10 20 PMOS 40X Leakage Variation (%) Delay Variation (%) 10 1 10 0 0 10 -10 -20 -1 10 Over 20% -30 -10 -8 -6 -4 -2 0 2 4 6 8 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 Length Variation (%) Length Variation (%) The small improvement of Δ L gate reduction can leads to significant decrease of delay and leakage variations. 5
Standard Cell Layout Optimization Since a lot of identical cells will be used repeatedly, any small changes can result in significant improvements. Restricted design-rules in industry [Choi’07 SPIE,Liebmann’09 SPIE] › Rule based and simple › Large number of rules and expensive rule checking › RDR is starting to fail in their attempt to use a discrete modeling approach on a continuous systems. Lithography model based optimization [Cote’04 ISQED,Tang’08 SPIE] › Robust layout for nominal lithography › No consider device criticality in circuit level › No single metric for both lithography proximity and process variation New model-based approach is needed. 6
Our Contributions Timing Criticality › The variation for a high sensitive device should be as small as possible. Process Criticality › Minimize the difference between fastest and slowest process corner Total Delay Sensitivity Modeling › Circuit Topological Delay Sensitivity › Lithography Proximity Induced Sensitivity › Process Variation Induced Sensitivity Delay, Leakage and Process Robust Layout 7
Device Criticality Based Sensitivity Delay variation for the delay arc, α due to variation, Δ L i : α ∂ d ∑ α ∆ = ∆ d L ∂ i L i i Total delay sensitivity index, Ψ : ∑ ∑ Ψ = ω α ⋅ ∆ α = σ ⋅ ∆ d L i α i The devices within the cell can be ranked. Circuit induced PMOS PMOS sensitivity σ NMOS NMOS σ = σ σ < σ NMOS PMOS NMOS PMOS 8 8
Lithography Proximity Sensitivity Transversal ( ΔL x ) variation and Longitudinal ( ΔL y ) variation Δe x ΔL x : EPE as a function of Δ e x . epe ∂ L ∆ = ∆ x , i L e printimage ∂ x , i x , i e x , i poly ΔL y is changed from different conduction Transversal ∂ ∂ L L ∝ ∆ ω y ∆ = ∆ = ∆ y f ( L , ) L e L ∂ x ∂ y y i e e y y ω is a weighting factor of narrow width effect Δe y Lithography proximity printimage Induced sensitivity γ poly 9 Longitudinal
Process Variation Induced Sensitivity Dose and focus errors are the dominant sources ∂ ∂ 2 L L ∆ = ∆ + ∆ 2 L % p p ∂ ∂ e f 2 ln p p e f Given focus level, Δ p f , ΔL can be simplified: ∂ L ∆ = + α ⋅ ∆ ⋅ ∆ 2 L [ 1 p ] % p ∂ f e ln p e F 0 ∂ L = ⋅ ∆ % p ∂ e ln p ∆ e p f ± Δ p e Process induced sensitivity Δ p f η symme metric 10
Three Metrics of Sensitivity Device Criticality σ ∑ Ψ = σ ⋅ ∆ L i i Lithography Proximity Sensitivity γ ∂ L ∆ = ∆ y L e ∂ i y e Slowest~+ η y Nominal~ γ Process induced sensitivity η Fastest~- η ∂ L ∆ = ⋅ ± ∆ L % p ∂ i e σ ln p ∆ e p f 11
Correlation Betw een γ and η The process sensitivity (η) is highly correlated with the lithography proximity sensitivity (γ). Once γ is calculated, we can estimate η. We should minimize the process gap (Slowest - Fastest). Slowest process corner Process Sensitivity ( η∆ p [%CD]) positive ∆ p 20 negative ∆ p linear fit 10 linear fit + γ 0 η smaller -10 nominal -20 -30 Fastest process corner − γ -30 -20 -10 0 10 20 η Proximity Sensitivity ( γ∆ e [%CD]) larger 12
Total Sensitivity ∂ ∂ L L ∑ Ψ = σ ⋅ ∆ = σ ⋅ ∆ + ⋅ ± ∆ i , j i L e % p ∂ ∂ i i i i y e e ln p j y e ∆ p f σ ( ) : device _ criticalit y = σ ⋅ γ + η i ∆ ± ∆ i i i γ e , % p y e : proximity _ sensitivit y i η : process _ sensitivit y i Device criticality aware layout Process-robust layout 13
Poly / Active Layer Optimization Poly corner to active ( PCA ) positive Δ L gate Poly line-end ( PLE ) negative Δ L gate Active corner to poly ( ACP ) positive Δ W gate Poly Layout Optimization Active Layout Optimization 14
Poly Layer Optimization PCA shows a convex form (-1/ √x) in our DRC range. PLE has a positive linear trend in a certain range. η ≥ ⋅ ∆ ⋅ γ + γ ≥ ⋅ + ⋅ + a PCA b PLE c d p e ij i i ij i ij 18 -4 60 Normalized ∆ L eff -0.9 15 Linear fit 50 Normalized ∆ d -5 Normailized ∆ L eff [nm] Normailized ∆ L eff [nm] Linear fit 12 Normalized ∆ d [%] 40 Normalized ∆ d [%] -1.2 30 9 -6 20 6 -1.5 10 Normalized ∆ L eff -7 3 Convex fit 0 Normalized ∆ d -1.8 Convec fit 0 -10 -8 0 10 20 30 40 50 60 70 6 9 12 15 18 Distance (Poly PAD to Active) [nm] Distance (Line-end to Active) [nm] PCA PLE 15
Poly Layer Optimization ∆ + ∆ min: d d Process Sensitivity ( η∆ p [%CD]) positive ∆ p ij , max ij , min 20 negative ∆ p linear fit ∑ 10 linear fit s.t.: ∆ ≥ σ γ + η d ( ) ij , max i ∈ ij ij j S ( i ) ∆ ∆ e ,% p y 0 ∑ ∆ ≤ σ γ − η d ( ) -10 ∈ ij , min i ij ij j S ( i ) ∆ ∆ e ,% p y -20 γ ≥ ⋅ + ⋅ + a PCA b PLE c -30 ij i i -30 -20 -10 0 10 20 η ≥ ⋅ ∆ ⋅ γ + Proximity Sensitivity ( γ∆ e [%CD]) d p e ij i ij The objective is to minimize the maximal delay variation. Since γ ij is convex, we can obtain optimal PCA and PLE. 16
Active Layer Optimization ACP has a positive linear trend with the distance of active corner to poly. ∑ ∆ ≥ σ γ d 2 min: Normalized ∆ L eff ij , max i ∈ ij 0.0 j S ( i ) ∆ e y Linear fit 0 Normalized ∆ d -0.5 Linear fit γ ≥ ⋅ + Normalized ∆ L eff [nm] s.t.: a ACP b Normalized ∆ d [%] -2 ij i -1.0 -4 -1.5 -6 The objective is to -2.0 minimize gate proximity. -8 -2.5 γ ij is linear, we can obtain -3.0 -10 20 30 40 50 optimal ACP. Distance (Avtive Rail to Poly) [nm] 17
Overall Flow Schematic Layout Statistical OPC/Lithography Characterization Total Sensitivity ( ) Device Criticality σ i, σ ⋅ γ + η i i i ∆ ∆ e ,% p y Poly Optimization Convex Formula Active Optimization Linear Formula Layout Extraction Cell Characterization 18
Exper eriment ment R Result ults: S : Setup up Impletemeted in Tcl/Perl Industrial 45nm ASIC designs Calibre-WB for model based OPC/Litho H-Spice for timing/characterization Two Layout Optimizations › Conventional restricted design rule (RDR) approach (CONV) › Total sensitivity based layout optimization (TSDFM) 19
Delay Variation Δ delay @best process is relatively low (around 3%) Up to 24% reduction in the delay difference between the fastest and the slowest process corner. 8% 16% The Delay Variation [%] 25 RDR 20 TSDFM 15 10 43% 5 0 CKT-BEST PV CKT-PV * Average delay for entire cells
Leakage Variation The local maximum leakage is decreased up to 91.9% in a cell and as much as 57.5% on average. Despite the small improvement of ΔL, we can see the huge amount of improvement on leakage current. Δ L Δ L Cell Leakage Leakage Improve CONV TSDFM % C1 -2.26 2.289E-08 -1.27 5.407E-09 85.12 C2 -1.28 5.434E-09 -0.94 4.619E-09 26.45 C3 -1.83 6.747E-09 -1.19 5.203E-09 35.13 C4 -2.90 3.082E-08 -1.08 4.940E-09 90.91 C5 -1.43 5.789E-09 -1.33 5.546E-09 7.07 C6 -1.86 6.808E-09 -0.54 3.639E-09 71.12 C7 -2.03 2.002E-08 -1.78 6.630E-09 75.78 C8 -2.76 2.917E-08 -1.18 5.178E-09 89.46 C9 -2.29 2.332E-08 -1.54 6.046E-09 82.38 C10 -2.79 2.945E-08 -2.54 2.637E-08 11.37 21
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