Multiple Gate CMOS and Beyond Dept. of EECS, KAIST Yang-Kyu Choi - PowerPoint PPT Presentation

Multiple Gate CMOS and Beyond Dept. of EECS, KAIST Yang-Kyu Choi

Outline 1. Ultimate Scaling of MOSFETs - 3nm Nanowire FET - 8nm Non-Volatile Memory Device 2. Multiple Functions of MOSFETs 3. Summary 2

CMOS Evolution Scenario G G S D S D Fin Fin Fin Buried Oxide All-around Ω -gate Bulk-single gate Double gate SOI single gate No report for Sub-50nm This L G =8nm L G =4nm L G =10nm L G =10nm IBM NEC AMD/Berkeley LETI Work IEDM 2003 IEDM 2003 IEDM 2003 VLSI 2005 3

ITRS Roadmap 2006 2008 2011 2013 2020 L G (nm) 28 22 16 13 5 Bulk SG 1.1 0.9 0.5 EOT (nm) DG 0.8 0.6 0.5 0.2 0.32 Bulk SG 0.15 I sd,leak ( µ A/ µ m) 0.1 0.11 0.11 DG 1570 2490 Bulk SG 1130 I d,sat 1899 (mA/mm) 2220 2981 DG Source: ITRS 2005 roadmap Solution exist Solution being pursued No known solution 4

All-Around Gate (AAG) FinFET • AAG-FinFET Source – L G =3nm Gate – W Fin =3nm – EOT(HfO 2 )=1.2nm Gate Drain • To fabricate sub-5nm silicon transistor, All-Around Gate (AAG) FinFET was proposed. 5

Process Flow of AAG-FinFET • (100) SOI wafer • Silicon body thinning • Fin patterning (dual-resist) • Sacrificial oxidation • Gate dielectric (HfO 2 ) • Poly-silicon deposition • Gate patterning (dual-resist) • Spacer formation • Source/Drain implantation • Spike annealing (1000 o C) • Forming gas annealing (450 o C) 6

3nm AAG FinFET: Silicon-Fin Silicon 20nm fin HfO 2 Poly-si S Source Source Gate Gate 3nm Buried oxide Gate Gate Drain Drain 5nm 3nm 5nm Y.-K. Choi et al., VLSI, 2006 7

3nm AAG FinFET: Gate Poly-si 5nm HfO 2 IFO 5nm Si 5nm Poly-si Poly-si Gate Source Source 3nm Gate Gate HfO 2 Gate Gate Drain Drain IFO Si 5nm Silicon fin 8

I-V of 3nm AAG FinFET 350 160 -3 10 Drain Current [ µ A/ µ m] Transconductance [ µ S/ µ m] Simulated V D =1.0V HfO 2 =1.4nm 140 300 Drain Current [A/ µ m] 0.6V Measured L G =3nm 120 -4 10 250 V D =0.2V W Fin =3nm 100 0.4V 200 80 -5 10 DIBL=230mV/V 150 60 SS=208 mV/dec V G =0.2V HfO 2 =1.4nm 100 40 -6 10 L G =3nm 20 50 W Fin =3nm 0 -7 10 0 -1.0 -0.6 -0.2 0.2 0.6 1.0 0.0 0.2 0.4 0.6 0.8 1.0 Gate Voltage [V] Drain Voltage [V] • Large DIBL and SS due to thick EOT – ITRS requirement: 0.5nm EOT for DG 9

Fundamental Limit of Scaling • Device scaling limit (Operating at 300K) – Heisenberg ’ s uncertainty principle – Shannon - von Neumann - Landauer (SNL) expression h h h = = = x SCALING min ∆ p 2 m E 2 m k T ln 2 c bit c B LIMIT = = 1 . 5 nm ( T 300 K ) 1.5 Fabricated 3nm all-around gate FinFET is approaching to this fundamental limit. 10 10

Nanowire Structure • Silicon nanowire non-volatile memory structure for ultimate scaling Poly-silicon Blocking oxide Nitride trap layer Si Tunneling oxide Buried Oxide 8nm Non-Volatile Memory Omega-shape gate ONO-structure 11 11

8nm Si Nanowire NVM Silicon Poly-silicon Gate Nanowire S (7/10nm) NO O S e - trap BOX Tunneling oxide sites Nitride trap layer Blocking oxide Gate Poly-silicon 10nm Y.-K. Choi et al., VLSI, 2007 12 12

8nm Si Nanowire NVM 8nm Gate 7/10nm 3.8nm Oxide 6.4nm 5.1nm Nitride 5.1nm Silicon 6.4nm 3.8nm T ONO =15nm > L G =8nm 13 13

8nm Silicon Nanowire NVM with ONO -4 -4 1x10 1x10 Drain Current [A/ µ m] ONO=3.8/6.4/5.1nm ONO=3.8/6.4/5.1nm Drain Current [A/ µ m] -5 -5 t Program =80 µ sec t Erase =80 µ sec 1x10 1x10 -6 -6 10 10 -10 -8V V ER =-12V Initial -7 -7 10 10 8V 10V Initial V PG =12V -8 -8 10 10 L G =8nm L G =8nm W NW =7nm W NW =7nm -9 -9 10 10 H NW =10.5nm H NW =10.5nm -10 -10 10 10 -4 -3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3 Gate Voltage [V] Gate Voltage [V] • 8nm L G with 7nm W NW using ONO-structure - Acceptable electrical performance by omega-gate - Wide hysteresis shows the probability of multi-level NVM 14 14

8nm Si Nanowire Memory 3.0 4.0 L G =8nm ONO=3.8/6.4/5.1nm 3.5 2.5 L G =8nm W NW =7nm 3.0 V PG =12V W NW =7nm H NW =10nm 2.0 2.5 ∆ V T [V] ∆ V T [V] 2.0 1.5 V ER =-8V V PG =10V 1.5 1.0 -10V 1.0 V PG =8V 0.5 0.5 V ER =-12V 0.0 0.0 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 Program Time [sec] Erase Time [sec] • 8nm NVM: V T window = 2V – Program @ +12V/1msec, Erase @-12V/1msec 15 15

Scaling Limit in NVM • Ultimately scaled NVM • Nanowire + SONOS T O/N/O =15nm > L g =8nm Scaling Limit ! Y.-K. Choi et. al., VLSI 2007 • Close to end-point of semiconductor memory 16 16

Where to Go? This Multi- Functioning Work ! Multi-Bit Down Scaling We are here We are here 17 17

Example of Fusion Memory (System in Package) DRAM DRAM NVM NVM SRAM SRAM . . . Wafer level • Increased volume • Complexity in assembly fusion !! • Chip-to-chip interference 18 18

Principal of SONOS Flash Memory Gate Gate control oxide ‘1’ nitride ‘0’ Drain current ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊕ ⊕ ⊕ ⊕ tunnel oxide ⊕ ⊕ ⊕ ⊕ ⊖ ⊖ ⊖ ⊖ ⊕ ⊕ S D S D ⊕ ⊕ Substrate Substrate < program > < erase > Gate Gate Gate voltage ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊕ ⊕ ⊕ ⊕ Features of flash ⊕ ⊕ ⊕ ⊕ S D S D • High density ↑ Substrate Substrate • Non-volatile ↑ < read ‘0’ > < read ‘1’ > • Speed ↑ 19 19

Principal of Capacitorless DRAM Gate Gate ⊖ ⊖ S D S D ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ Buried oxide Buried oxide Substrate Substrate < program > < erase > Gate Gate S D S D ⊕ ⊕ ⊕ ⊕ Buried oxide Buried oxide Substrate Substrate Source : IEEE spectrum Dec. 2008 Source : IEEE spectrum Dec. 2008 < read ‘1’ > < read ‘0’ > Features of 1T-DRAM Drain current • High speed ↑ ‘1’ • 2x denser than 1T/1C DRAM ↑ ‘0’ • 5x denser than SRAM ↑ Time • Volatile ↓ 20 20

Basis of URAM Operation (1) Flash Memory Mode Gate voltage flash program - Program : FN tunneling/HEI capacitorless - Erase : FN tunneling/HHI 1T-DRAM (High gate & drain voltage) program capacitorless 1T-DRAM Capacitorless 1T-DRAM Mode erase Drain voltage - Program : Impact ionization - Erase : Forward junction current (Low gate & drain voltage) Disturbance Issue flash erase - Periodical refresh 21 21

Multi-Function (URAM) Operation Flash Memory electron DRAM hole Gate Oxide Nitride Oxide Drain Source 드레인 Quantum Barrier 22 22

Family of URAM S. Okonin et.al. , SOI conf. , 2001 R. Ranica et.al. , VLSI symp. , 2004 23 23

Process Flow (1) SOC Substrate SOI Substrate Si Si Si:C Buried oxide Si substrate Si substrate • Initial SOI substrate • Initial bulk substrate • Si:C epitaxial growth • Si epitaxial growth SON Substrate SOG Substrate Si Si Si:Ge n-well Si substrate Si substrate • Initial bulk substrate • Initial bulk substrate • Buried n-well implantation • Si:Ge epitaxial growth • p-body implantation • Si epitaxial growth 24 24

Process Flow (2) Puntch stop implantation fin Active fin lithography Photoresist trimming Hole barrier layer Fin patterning Si substrate HDP oxide deposition fin fin Oxide CMP SiO 2 SiO 2 SiO 2 SiO 2 Oxide recess formation Hole barrier layer Hole barrier layer Si substrate Si substrate 25 25

Process Flow (3) O/N/O formation Gate Gate fin fin Poly-Si deposition SiO 2 SiO 2 SiO 2 SiO 2 Hole barrier layer Hole barrier layer Si substrate Si substrate Gate patterning Gate Gate S/D implantation fin fin Activation SiO 2 SiO 2 SiO 2 SiO 2 Hole barrier layer Hole barrier layer Forming gas annealing Si substrate Si substrate 26 26

URAM on SOI 27 27

Cross sectional view of URAMs URAM URAM URAM URAM on SOI on SiC on On SiGe Buried N-well 28 28

I D -V G Characteristics V D = 1V -5 10 Drain current, V D (A) -6 10 I D -7 10 SOI -8 10 SOC SOG -9 10 SON -10 10 -11 10 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Gate voltage, V G (V) • Superior device performances are result of the 3D nature. 29 29

I D -V D Characteristics (Kink) SOC SOI SON SOG 30 30

P/E in NVM Program Erase • P/E sensing windows are acceptable. 31 31

Reliability in NVM Retention Endurance • Data retention and endurance are acceptable. 32 32

Capacitorless 1T-DRAM in SOI PD URAM FD URAM 80 70 Source current, I S ( µ A) 60 0.8V ∆ I s =20 µΑ 50 SOI URAM ∆ I s =7 µΑ 40 0.7V 30 0.6V 20 80msec Conventional 10 FinFET SONOS 0 0 50 100 150 200 Time, t (msec) < Measurement Results > < Potential Profile > • Proposed SOI URAM exhibits wider sensing current window. Y.-K. Choi et. al., IEDM 2007 33 33

Capacitorless 1T-DRAM in SON bulk MOSFET Y.-K. Choi et. al., VLSI 2008 32 28 Sensing current, I S ( µ A) V SUB =0.5V 24 20 SON URAM 16 ∆ I S =7 µ A V SUB =0.3V 12 ∆ I S =4 µ A 8 V SUB =0V 4 0 1 2 3 4 5 Time, t (msec) < Measurement Results > < Excess Hole Concentration > • Capacitorless 1T-DRAM works in SON floating substrate. 34 34