Lecture 12 Logistics HW4 was due yesterday HW5 was out yesterday - PDF document

Lecture 12 � Logistics � HW4 was due yesterday � HW5 was out yesterday (due next Wednesday) � HW5 was out yesterday (due next Wednesday) � Feedback: thank you! � Things to work on: Big picture, Book chapters, Exam comments � Last lecture � Adders � Today � Clarification of Adders Cl ifi ti f Add � Summary of Combinational Logic � Introduction to Sequential Logic � The basic concepts � A simple example CSE370, Lecture 13 12 1 Adders allow computers to add numbers 2-bit ripple-carry adder A B A 1 B 1 A 2 B 2 1-Bit Adder XOR A XOR B 32 C in C out C in C out Sum 0 Cin 33 AND2 B C in Cin C out 11 AND2 OR3 Sum 1 Sum 2 A Cout Ci Cin 12 14 AND2 A B 13 Overflow Sum CSE370, Lecture 13 11 12 2

Problem: Ripple-carry delay � Carry propagation limits adder speed (we want to add fast) Cin XOR XOR @0 A S0 @2 XOR A0 @0 B 32 B0 C1 @2 Sum @2N Cin 33 @2N+1 A1 S1 @3 AND2 @0 B1 C2 @4 B @2N Cin 11 AND2 OR3 @2N+2 @2N 2 A2 A2 S2 @5 S2 @5 @0 @0 A A B2 C3 @6 Cout @2N Cin 12 14 AND2 @0 A A3 S3 @7 B3 Cout @8 @0 B 13 C out takes two gate delays C in arrives late CSE370, Lecture 13 11 12 3 One Solution: Carry lookahead logic � Get Pi (propagate) and Gi (generate) Cin XOR Pi @1 @0 @0 A A XOR @2 @0 B 32 S0 @2 A0 P0 Sum @3 @2N Cin B0 C1 @2 G0 33 @2N+1 @4 AND2 @0 A1 S1 @3 B P1 B1 C2 @4 @3 @2N G1 Cin 11 AND2 OR3 @2N+2 @0 A A2 A2 S2 @5 S2 @5 @ @4 Cout Cout P2 P2 @2N Cin 12 14 B2 C3 @6 G2 @3 AND2 C 2 = G 1 + P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 0 @0 A @4 Gi A3 S3 @7 @0 C 3 = G 2 + P 2 C 2 P3 B 13 B3 C4@8 G3 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 1 = G 0 + P 0 C 0 @3 C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 CSE370, Lecture 13 12 4

Cascaded carry-lookahead adder (in your HW5) � 4 four-bit adders with internal carry lookahead � Second level lookahead extends adder to 16 bits 4 4 4 4 4 4 4 4 A[15-12] B[15-12] A[11-8] B[11-8] A[7-4] B[7-4] A[3-0] B[3-0] C12 C8 C4 C0 4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder @0 P G P G P G P G 4 4 4 4 S[15-12] S[11-8] S[7-4] S[3-0] @8 @8 @7 @4 @3 @2 @2 @3 @2 @3 @2 @3 @5 @5 @4 P3 G3 P2 G2 C2 P1 G1 C1 P0 G0 C3 C16 C0 C4 C0 Lookahead Carry Unit @5 @0 P3-0 G3-0 @3 @5 CSE370, Lecture 13 11 12 5 Another solution: Carry-select adder � Redundant hardware speeds carry calculation � Compute two high-order sums while waiting for carry-in (C4) � Select correct high-order sum after receiving C4 � Select correct high-order sum after receiving C4 @3 C8 0 4-bit adder adder [7:4] low I 0 @4 S @3 Z @4 @6 @3 C8 1 4-bit adder I 1 adder @4 [7:4] high @4 @3 1 0 1 0 1 0 1 0 1 0 C0 C4 4-Bit Adder five [3:0] 2:1 muxes @5 C8 S7 S6 S5 S4 S3 S2 S1 S0 @6 @4 CSE370, Lecture 13 12 11 6

We've finished combinational logic... � What you should know � Twos complement arithmetic � Truth tables � Truth tables � Basic logic gates � Schematic diagrams � Timing diagrams � Minterm and maxterm expansions (canonical, minimized) � de Morgan's theorem � AND/OR to NAND/NOR logic conversion � K maps, logic minimization, don t cares � K-maps, logic minimization, don't cares � Multiplexers/demultiplexers � PLAs/PALs We had no way to store memory: � ROMs When the input changed, the output changed � Adders Next: Sequential logic can store memory… CSE370, Lecture 13 12 11 7 Sequential Logic (next 5 weeks!) � We learn the details � Latches, flip-flops, registers (storage) � Shift registers counters (we can count now!) � Shift registers, counters (we can count now!) � State machines � Timing and timing diagrams � timing more important than combinational logic � Synchronous and asynchronous inputs � Metastability (problem!) � Moore and Mealy machines (types of state machines) � More... CSE370, Lecture 13 12 8

Sequential versus combinational A C B B clock Apply fixed inputs A, B Wait for clock edge Observe C Wait for another clock edge Observe C again Ob C i Combinational: C will stay the same Sequential: C may be different CSE370, Lecture 13 12 9 Sequential versus combinational (again) � Combinational systems are memoryless � Outputs depend only on the present inputs Inputs System Outputs � Sequential systems have memory � Outputs depend on the present and the previous inputs Inputs System Outputs Feedback CSE370, Lecture 13 12 10

Synchronous sequential systems � Memory holds a system’s state � Changes in state occur at specific times � A periodic signal times or clocks the state changes � A periodic signal times or clocks the state changes � The clock period is the time between state changes A C B State changes occur clock at rising edge of clock pulsewidth duty cycle = pulsewidth/ period (here it is 50% ) clock period CSE370, Lecture 13 12 11 Steady-state abstraction � Outputs retain their settled values � The clock period must be long enough for all voltages to settle to a steady state before the next state change settle to a steady state before the next state change A C B clock Clock hides transient behavior clock C Settled value CSE370, Lecture 13 12 12

What did I just say about sequential logic? � Has clock � Synchronous = clocked � Exception: Asynchronous � Exception: Asynchronous � Has state � State = memory � Employs feedback � Assumes steady-state signals � Signals are valid after they have settled � Signals are valid after they have settled � State elements hold their settled output values CSE370, Lecture 13 12 13 Example: A sequential system � Door combination lock � Enter 3 numbers in sequence and the door opens � If there is an error the lock must be reset � If there is an error the lock must be reset � After the door opens the lock must be reset � Inputs: Sequence of numbers, reset � Outputs: Door open/close � Memory: Must remember the combination CSE370, Lecture 13 12 14

Understand the problem � Consider I/O and unknowns � How many bits per input? � How many inputs in sequence? � How many inputs in sequence? � How do we know a new input is entered? � How do we represent the system states? new value reset clock open/closed CSE370, Lecture 13 12 15 Implement using sequential logic � Behavior � Clock tells us when to look at inputs � After inputs have settled � After inputs have settled � Sequential: Enter sequence of numbers � Sequential: Remember if error occurred � Need a finite-state diagram new value reset � Assume synchronous inputs � State sequence � Enter 3 numbers serially � Remember if error occurred b f d clock � All states have outputs � Lock open or closed open/closed CSE370, Lecture 13 12 16

Finite-state diagram � States: 5 � Inputs: reset, new, results of � Each state has outputs comparisons � Assume synchronous inputs y p � Outputs: open/closed � O t t / l d We use state diagrams to represent sequential logic ERR System transitions between closed finite numbers of states C1!= value C2!= value C3!= value & new & new & new & new S1 S2 S3 OPEN reset closed closed closed open C1= = value C2= = value C3= = value & new & new & new not new not new not new CSE370, Lecture 13 12 17 Separate data path and control � Data path � Control � Stores combination � Finite state-machine controller � Compares inputs with � Compares inputs with � Control for data path � Control for data path combination � State changes clocked new reset C1 C2 C3 4 4 4 mux control multiplexer multiplexer 4 controller clock value comparator equal 4 open/closed CSE370, Lecture 13 12 18

Refine diagram; generate state table ERR � Refine state diagram to closed include internal structure not equal not equal not equal & new not equal & new & new S1 S2 S3 OPEN closed closed closed reset open mux= C1 equal mux= C2 equal mux= C3 equal & new & new & new not new not new not new next reset reset new new equal equal state state state state mux mux open/closed open/closed � Generate 1 – – – S1 C1 closed state table 0 0 – S1 S1 C1 closed 0 1 0 S1 ERR – closed 0 1 1 S1 S2 C2 closed ... 0 1 1 S3 OPEN – open ... CSE370, Lecture 13 12 19