ENEL 353 F13 Section 02 Slides for Lecture 35 slide 2/33 ENEL 353 F13 Section 02 Slides for Lecture 35 slide 3/33 Previous Lecture Today’s Lecture Slides for Lecture 35 ENEL 353: Digital Circuits — Fall 2013 Term Completion of coverage of memory arrays, including use of Steve Norman, PhD, PEng Counters and shift registers. ROM circuits to implement combinational logic functions. Introduction to memory arrays. Electrical & Computer Engineering Schulich School of Engineering Related reading in Harris & Harris: Section 5.5 University of Calgary 2 December, 2013 slide 4/33 slide 5/33 slide 6/33 ENEL 353 F13 Section 02 Slides for Lecture 35 ENEL 353 F13 Section 02 Slides for Lecture 35 ENEL 353 F13 Section 02 Slides for Lecture 35 Quick review: The concept of a memory array Bit cells, wordlines, and bitlines More about wordlines Each bit stored within a memory These are the essential inputs 4 columns bitline . . . Address bitline M − 1 bitline 1 bitline 0 array in stored in a tiny circuit and outputs of a memory 111 1 0 1 0 wordline wordline i element called a bit cell . array . . . 110 0 1 1 1 8 4-bit words in 8 rows stored stored . . . stored stored Signalling to a bit cell is done bit bit bit bit 101 0 0 0 0 through two wires: a wordline N Address Array and a bitline . 100 0 1 1 0 Each wordline is connected to all of the bits within a single Wordline: Each wordline is connected to all of the bits within word. 011 1 1 1 1 a single word. M Normally one wordline is ON and all the others are OFF, so 010 0 1 0 0 Bitline: Each bitline is connected to all of the bits within a Data that a single word is selected for reading or writing. single column. 001 1 1 0 1 What kind of circuit element is perfectly suited for converting For the example at left, with 32 If a memory array has an 8-bit address bus and a 9-bit data 000 0 0 1 1 an address input into the correct set of wordline signals? stored bits, what are N and M? bus, how many wordlines are there? How many bitlines? ENEL 353 F13 Section 02 Slides for Lecture 35 slide 7/33 ENEL 353 F13 Section 02 Slides for Lecture 35 slide 8/33 ENEL 353 F13 Section 02 Slides for Lecture 35 slide 9/33 Organization of a 4 × 3 memory array Dot notation for ROM circuits ROM-based implementation of logic functions 2:4 4 columns Decoder Address bitline 2 bitline 1 bitline 0 A ROM circuit can be thought of as a “truth table baked into Often a ROM is drawn showing wordline 3 11 111 1 0 1 0 silicon.” only its decoder, the wordlines stored stored stored Address 2 8 4-bit words in 8 rows bit = 0 bit = 1 bit = 0 and bitlines, and some dots. 110 0 1 1 1 This way of thinking about ROM leads to the conclusion that wordline 2 10 any combinational logic element can be implemented as a A dot at a wordline-bitline 101 0 0 0 0 stored stored stored ROM circuit. bit = 1 bit = 0 bit = 0 wordline 1 crossing point indicates a 01 100 0 1 1 0 stored 1 . No dot at a crossing stored stored stored 2 N × M bit = 1 bit = 1 bit = 0 point indicates a stored 0 . 011 1 1 1 1 wordline 0 ROM 00 N Let’s draw a dot-notation 010 0 1 0 0 stored stored stored N M Address C bit = 0 bit = 1 bit = 1 L diagram for ROM with the can be implemented as 001 1 1 0 1 Data contents of the table to the Data 2 Data 1 Data 0 000 0 0 1 1 M right. Image is Figure 5.42 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed. , c � 2013, Elsevier, Inc.
ENEL 353 F13 Section 02 Slides for Lecture 35 slide 10/33 ENEL 353 F13 Section 02 Slides for Lecture 35 slide 11/33 ENEL 353 F13 Section 02 Slides for Lecture 35 slide 12/33 ROM-based logic: Examples Why use ROMs for combinational logic? Why not? NMOS transistors NMOS transistors are one of the Let’s implement the following combinational elements using two main kinds of building blocks drain ROM circuits with appropriate dimensions. Using a ROM structure for N -input, M -output logic is for CMOS circuits. An NMOS sometimes a good design choice, and sometimes not. I DS 1. F = A ⊕ B ; G = ( A ⊕ B ); H = A + B . transistor has the four terminals shown, but in CMOS the bulk is gate bulk Let’s do this one by using algebra to express each of “Custom” solutions with logic gates tend to use less chip area assumed to be connected to F , G , and H as a sum of minterms. and less power than ROM-based solutions, and can be much source faster. ground and is usually not shown 2. E = ABC ; in circuit diagrams. However, the design effort needed for a ROM-based solution is F = A ⊕ B ; close to zero, so it may be a good choice if area, power, and The relationship of the current I DS to the voltages at the gate, G = AB + AC + BC ; speed constraints are not pressing. drain and source is quite complex. (See ENCM 467.) But a H = A + B + C . simple, crude model helps explain how bit cells work in Let’s do this one by making a truth table. memory arrays. slide 13/33 slide 14/33 slide 15/33 ENEL 353 F13 Section 02 Slides for Lecture 35 ENEL 353 F13 Section 02 Slides for Lecture 35 ENEL 353 F13 Section 02 Slides for Lecture 35 NMOS transistor with V gate close to zero NMOS transistor with V gate close to V DD A ROM circuit made with NMOS transistors V DD The second part of our simple, crude model is not very R R R accurate , but good enough to get a qualitative feel for how A 2:4 decoder drives the word- The first part of our simple, crude model is actually quite line 3 bit cells work. wordlines, but is not accurate. shown here, to save When the gate voltage is close to zero, the drain-to-source When the gate voltage is close to the power supply voltage, word- space on this slide. the drain-to-source connection is somewhat like a small line 2 connection is like an open switch—no current can flow. resistance in series with a closed switch—current flows if What happens to the drain drain word- V drain � = V source . bitlines if wordline 2 is line 1 I DS ? I DS = 0 turned ON and the other drain drain three wordlines are OFF? V gate ≈ 0 word- I DS ? line 0 If V drain � = V source , What are the contents of source source V gate ≈ V DD then I DS � = 0. this ROM array? bit- bit- bit- source source line 2 line 1 line 0 ENEL 353 F13 Section 02 Slides for Lecture 35 slide 16/33 ENEL 353 F13 Section 02 Slides for Lecture 35 slide 17/33 ENEL 353 F13 Section 02 Slides for Lecture 35 slide 18/33 Programmable ROM circuits Much cooler than a ROM circuit that can be programmed What’s left in ENEL 353 in Fall 2013? only once is a ROM circuit that can programmed, then erased, and then re-programmed, many, many times. The ROM circuit on the previous slide can only be made in a Production of this kind of erasable, programmable ROM semiconductor fab , which is a fancy name for “chip factory”. Tutorial Tue Dec 3. Problems on some or all of the circuit is a huge industry , based on one key electronic device: following topics: FSMs, timing constraints with clock skew, It’s obviously useful to have circuits that have the essential the floating-gate transistor . counters, shift registers, memory arrays. ROM properties—contents not lost when power is turned off, Some of the many products that depend utterly on Examinable material in lecture Wed Dec 4. PLAs (Harris contents won’t change when normal digital logic voltages are floating-gate transistors are . . . and Harris Section 5.6.1). applied—but are also programmable . ◮ USB “thumb” drives Non-examinable material in lecture Wed Dec 4. Topics A programmable ROM is a ROM circuit into which 1’s and 0’s ◮ SD cards and related storage techologies are yet to be determined. can be written after the circuit is fabricated. ◮ solid-state drives in laptop and desktop computers Lecture Fri Dec 6. Comments about the final exam, and See Figure 5.51 and related discussion in Harris & Harris for ◮ smartphones and tablet computers review of course content. explanation of one-time-programmable ROM circuits based on fuses that are either blown or intact. Some slides at the end of this slide set give a brief explanation of floating-gate transistor behaviour.
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