ENEL 353 F13 Section 02 Slides for Lecture 27 slide 2/19 ENEL 353 F13 Section 02 Slides for Lecture 27 slide 3/19 Previous Lecture Today’s Lecture Slides for Lecture 27 ENEL 353: Digital Circuits — Fall 2013 Term Review of the steps involved in designing a Moore FSM. A “divide-by-3 counter” FSM design problem, solved with Steve Norman, PhD, PEng Detailed discussion of an example from the textbook: the binary state encoding, and solved again with “one-hot” encoding. traffic light controller FSM. Electrical & Computer Engineering Schulich School of Engineering Introduction to “sequence detection” problems, and solution University of Calgary using Moore and Mealy FSMs. 13 November, 2013 Related reading in Harris & Harris: Sections 3.4.2, 3.4.3 slide 4/19 slide 5/19 slide 6/19 ENEL 353 F13 Section 02 Slides for Lecture 27 ENEL 353 F13 Section 02 Slides for Lecture 27 ENEL 353 F13 Section 02 Slides for Lecture 27 Moore FSM structure of traffic light controller Timing diagram for the traffic light controller FSM Review of steps in design of a Moore FSM (slide repeated from previous lecture) (slide repeated from previous lecture) CLK L A 1 S ′ S 1 Figure 3.27 on page 128 of Harris & Harris is an excellent 1 timing diagram showing behaviour of the FSM over ten This is what we went through for the traffic light controller L A 0 example. The same sequence of steps is more or less example clock cycles. T A applicable to all FSM design problems. S ′ S 0 0 L B 1 There’s too much detail in the diagram to make a legible slide r The steps are listed on the next two slides. T B from it. reset L B 0 Please study the diagram and the related discussion on pages 127 and 129 carefully! It really helps in explaining typical FSM S 0 output logic operation as time progresses. S 1 next state logic ENEL 353 F13 Section 02 Slides for Lecture 27 slide 7/19 ENEL 353 F13 Section 02 Slides for Lecture 27 slide 8/19 ENEL 353 F13 Section 02 Slides for Lecture 27 slide 9/19 Moore FSM steps, slide 1 of 2 Moore FSM steps, slide 2 of 2 Next FSM Example: A “divide-by-3 counter” ◮ Update the state transition table to reflect the state This example is taken from Section 3.4.2 of Harris & Harris. ◮ Start with a word description of what the FSM will do. encoding. The result is a truth table for the next state We’ll use the example logic . Use K-maps or some other method to find If necessary, refine the word description so that it is ◮ to review the steps in designing an FSM, starting from a complete and unambiguous . equations for the next state logic. word description of system behaviour; ◮ Make an output table to list what the output bits are ◮ Use the word description to create a state transition ◮ to illustrate how the choice of state encoding may for each the state encodings. Use K-maps or some other diagram . influence the relative complexity of next state and output method to find equations for the output logic . ◮ Use the state transition diagram to make a state logic. ◮ Design combinational logic to implement the next state transition table . Word description of the divide-by-3 counter: The only and output equations. If you’re taking a course such as ◮ Decide on a state encoding : Each state must be ENEL 353, make a schematic. (In the “real world”, it’s inputs are clock and reset signals. The output should be 1 represented by a unique sequence of 1’s and 0’s. more likely that you would describe the next state and during every third cycle of the input clock, and 0 during other output logic in a language such as VHDL.) cycles of the input clock.
ENEL 353 F13 Section 02 Slides for Lecture 27 slide 10/19 ENEL 353 F13 Section 02 Slides for Lecture 27 slide 11/19 ENEL 353 F13 Section 02 Slides for Lecture 27 slide 12/19 Divide-by-3 counter: “A divide-by-N counter has one output Divide-by-3 counter with binary state encoding Waveforms and a state transition diagram and no inputs.” CLK The title of this slide is a quote from page 129 of Harris and Y Harris. (a) Let’s finish the design of the counter using unsigned binary Does it make sense to say there are no inputs? Every FSM encoding for the states S0, S1, and S2. Reset needs a clock input. And the state transition diagram for the Unlike what is done in the textbook, we’ll put the unused state S0 S1 S2 divide-by-3 counter also shows a reset input. 11 into our truth tables with the goal of using don’t-care Y : 1 Y : 0 Y : 0 outputs to simplify the next-state and output equations. Important: In discussion of FSMs, it’s traditional to count the number of inputs as the number of system input signals used by the next state logic . For whatever reason, important (b) input signals—such as CLK and reset—that go straight to the Image is taken from Figure 3.28 from Harris D. M. and Harris S. L., state register do not count in the number of FSM inputs. Digital Design and Computer Architecture, 2nd ed. , c � 2013, Elsevier, Inc. slide 13/19 slide 14/19 slide 15/19 ENEL 353 F13 Section 02 Slides for Lecture 27 ENEL 353 F13 Section 02 Slides for Lecture 27 ENEL 353 F13 Section 02 Slides for Lecture 27 Divide-by-3 counter with one-hot encoding Sequence detection problems Useful assumptions for sequence detection problems One-hot state encoding requires one flip-flop for each state. In Most textbooks on digital design present several FSM design any state, a single state bit is TRUE and all the others are problems that are worded something like this example: First, let’s assume that the clock period is long compared FALSE. “Design an FSM that will have an output of 1 only when the to switching times for the available circuit elements. That way, input is 0, but was 1 for the previous three clock cycles.” we can ignore timing problems caused by excessive delays in One-hot state encodings for a system with three states: circuit elements. 001, 010, 100. Example 3.7 from Harris & Harris: “Alyssa P. Hacker owns a pet robotic snail with an FSM brain. The snail crawls from left Second, let’s assume that the input will be “reasonable”, in One-hot state encodings for a system with four states: to right along a paper tape containing a sequence of 1’s the following senses: 0001, 0010, 0100, 1000. and 0’s. On each clock cycle, the snail crawls to the next bit. ◮ The input makes at most one 0 → 1 or 1 → 0 transition Let’s complete the divide-by-3 FSM design using one-hot state The snail smiles when the last two bits it has crawled over are, within any single clock cycle. encoding, then make a few remarks. from left to right, 01. Design the FSM [. . . ]” ◮ The input never makes a 0 → 1 or 1 → 0 transition We’ll assume that we can build a state register out of Problems of this kind are great practice for students, because really near in time to a rising clock edge. (This eliminates resettable DFFs and/or settable DFFs, whatever is needed to solving them requires careful thought about states and state uncertainty about DFF D input values when those values make the reset logic work. transitions. are being copied to DFF Q outputs.) ENEL 353 F13 Section 02 Slides for Lecture 27 slide 16/19 ENEL 353 F13 Section 02 Slides for Lecture 27 slide 17/19 ENEL 353 F13 Section 02 Slides for Lecture 27 slide 18/19 Which of A , B , C and D are “reasonable” inputs Review: Moore and Mealy FSM structures A sequence detection problem for sequence detection? Which is which? How can you tell? Problem statement: Design an FSM to detect the following (a) sequence of bits on the FSM input: 1 for three clock cycles CLK 1 M CLK next next followed by a 0. The output should be 1 when the sequence inputs 0 k k N state state output state outputs has been detected and 0 at other times. 1 logic logic A 0 We’ll consider both Moore and Mealy FSM designs. 1 B For each of the Moore and Mealy designs, what does the 0 (b) 1 problem statement mean, in terms of the current input value C CLK 0 and the values of the input at recent clock edges? 1 D output N inputs M next outputs Let’s make a timing diagram to be really clear about how the 0 next logic t 0 t 1 t 2 t 3 t 4 k state k state state Moore and Mealy outputs will react to a typical input signal. logic
ENEL 353 F13 Section 02 Slides for Lecture 27 slide 19/19 Upcoming topics Moore and Mealy state transition diagrams for the sequence detection problem. Completion of next state and output logic design for the Mealy FSM. Factoring of FSMs. Reverse-engineering an FSM: Given a circuit, find a word description of what the FSM does. Related reading in Harris & Harris: Sections 3.4.3–3.4.6
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