ENEL 353 F13 Section 02 Slides for Lecture 33 slide 2/23 ENEL 353 F13 Section 02 Slides for Lecture 33 slide 3/23 Previous Lecture Today’s Lecture Slides for Lecture 33 ENEL 353: Digital Circuits — Fall 2013 Term Completion of a timing analysis example. The problem of asynchronous inputs to synchronous systems; Introduction to clock skew . solution with synchronizer circuits. Steve Norman, PhD, PEng Adjustment of setup and hold time constraint inequalities Some insight into where metastability and setup times come to account for clock skew. Electrical & Computer Engineering from. Schulich School of Engineering University of Calgary What can happen when setup and hold time constraints are violated? Related reading in Harris & Harris: Sections 3.4.4–3.4.5. 27 November, 2013 Introduction to metastability . slide 4/23 slide 5/23 slide 6/23 ENEL 353 F13 Section 02 Slides for Lecture 33 ENEL 353 F13 Section 02 Slides for Lecture 33 ENEL 353 F13 Section 02 Slides for Lecture 33 Preventing metastability from causing circuit Examples of asynchronous inputs An example FSM with an asynchronous input failure In each of the systems below, A is what is called an If we don’t know anything at all about when edges on A might asynchronous input . . . A single DFF going metastable for a fraction of a clock cycle appear relative to edges on CLK, this is a bad design . . . CLK1 CLK2 may cause a synchronous system to behave incorrectly for a CLK CLK much longer time period, and may even cause the system to button synchro- synchro- freeze completely. next A nous nous A output A synchronous state Y One essential step in system 1 system 2 logic CLK logic system reducing the risk of CLK1 and CLK2 are problems is, as we’ve just unrelated , with different seen, careful timing analysis C L Why is it impossible to design the next state logic to prevent frequencies. of paths like this . . . disastrous metastability in the state register? On the left, the system can’t control when a human might But what about system inputs? Edges on inputs can have To greatly reduce the risk, A can be passed though a press or release the button. On the right, there will be no completely unpredictable timing relative to edges on the the predictable relationship between edges on A and edges synchronizer circuit , as shown on the next slide . . . system clock! on CLK2. ENEL 353 F13 Section 02 Slides for Lecture 33 slide 8/23 ENEL 353 F13 Section 02 Slides for Lecture 33 slide 9/23 slide 7/23 Detailed analysis of t res and synchronizers Some insight into circuits, setup times, and CLK metastability n1 n2 next In Sections 3.4.4–3.4.6, Harris and Harris present a formula for A output state the probability distribution of t res : Y logic logic FF1 FF2 � − t � P ( t res > t ) = T 0 synchronizer exp circuit T C τ The rest of the slides in this lecture are not exam material in Suppose the next state logic has been designed so that its t pd They go on to use that probability distribution to derive a ENEL 353 in Fall 2013. and t cd meet setup and hold constraints for the state register. formula for MTBF (mean time between failures) of They are intended to provide some insight into why latches synchronizer circuits. Recall that t res is the resolution time for a DFF or register. and flip-flops must have setup times, and why latches and In ENEL 353 in Fall 2013, we are not going to cover that flip-flops can go metastable. Suppose that a detailed transistor-level model says that it is material, and you will not be tested on it on the final exam. extremely unlikely that it will ever happen that t res > 0 . 5 T C . You are expected to understand the qualitative ideas about Let’s give an approximate, qualitative argument that there is metastability and synchronizers presented in Sections 3.4.4 very little risk of metastability in the state register. and 3.4.5.
ENEL 353 F13 Section 02 Slides for Lecture 33 slide 10/23 ENEL 353 F13 Section 02 Slides for Lecture 33 slide 11/23 ENEL 353 F13 Section 02 Slides for Lecture 33 slide 12/23 Static behaviour of CMOS NOT, NOR, and NAND Static solutions for some bistable circuits Static solutions for bistable circuits, continued gates gate 1 For each of the circuits, there are The upper-left and Q three static conditions that satisfy If we slowly vary the voltage at A in each of the circuits lower-right solutions are the QN input/output voltage relationships for V DD below, and measure the voltage at Y as we go, we’ll see an gate 2 voltage at QN stable solutions predicted both gates . . . gate 2 input/output relationship that looks something like the graph gate 1 by Boolean algebra: 0 sketched to the right. Q V DD (Q , QN) = (0 , 1) and voltage at QN gate 2 (Q , QN) = (1 , 0). A Y V DD gate 1 QN voltage at Y Boolean algebra only works 0 0 gate 2 A with 1’s and 0’s, so cannot Y 0 V DD 1 gate 1 gate 1 predict the metastable Q voltage at Q 0 solution in the middle of the 0 0 V DD graph. 0 V DD Y QN voltage at Q voltage at A 1 A gate 2 slide 13/23 slide 14/23 slide 15/23 ENEL 353 F13 Section 02 Slides for Lecture 33 ENEL 353 F13 Section 02 Slides for Lecture 33 ENEL 353 F13 Section 02 Slides for Lecture 33 Let’s look at what happens in the master latch when there is Dynamic behaviour of bistable circuits Metastability in a D flip-flop an edge on D just before a rising edge on CLK. Static analysis shows us only what the possible solutions are We studied this design in lectures and also in Lab 4. It’s not D R M when dV / dt = 0 for both gate outputs, and does not tell us Q M CLK how D flip-flops are constructed in most modern integrated how voltages might change as a function of time. circuits, but the design is relatively easy to understand. D Transistor physics and circuit theory, beyond what has been master D latch slave D latch R M taught to year 2 ENEL and ENSF students, says . . . D R M QN M S M Q M ◮ The static solutions that are identified by Boolean algebra CLK S M Q FF are stable equilibrium points . If a bistable circuit is in In an ideal SR latch, (Q M , QN M ) will go to (1 , 0) because of one of its stable states, moderate amounts of electrical the pulse on S M . But in a real SR latch, the width of the noise will not move the state very far away from that QN M S M pulse matters. stable state. CLK A wide pulse will make the latch “do the right thing.” ◮ The metastable state of a bistable circuit is an unstable Reminder: Because CLK passes through a NOT gate before equilibrium point . A very tiny amount of electrical A very narrow pulse will not decrease the voltage at QN M entering the master latch, the master latch is transparent noise will rapidly drive the circuit from there into one or very much, and the voltage at Q M won’t change at all. when CLK is LOW. the other of its stable states. (Q M , QN M ) will settle back to (0 , 1). ENEL 353 F13 Section 02 Slides for Lecture 33 slide 16/23 ENEL 353 F13 Section 02 Slides for Lecture 33 slide 17/23 ENEL 353 F13 Section 02 Slides for Lecture 33 slide 18/23 Now let’s have another look at the slave latch . . . Setup time in a modern DFF master D latch slave D latch D R M D R M Below is a D latch suitable for use as the master latch in a CLK Q M Q M Q FF DFF. Switches S1 and S2 are implemented in CMOS using D simple two-transistor devices called transmission gates . R M S1 I1 I2 Q M QN M QN M n1 S M D S M CLK S M CLK S2 CLK CLK QN M I3 If the width of the pulse on S M is “perfectly wrong” the When CLK is HIGH, the slave latch is supposed to be voltages at Q M and QN M will both be near 0 . 5 V DD when the transparent. But if Q M ≈ 0 . 5 V DD , both AND gates in the pulse ends. That gives the pair of NOR gates a chance to go slave have “forbidden zone” inputs, and we cannot rely on Q FF CLK CLK metastable! to have any particular value. CLK S1 S2 latch condition If it’s still true that Q M ≈ 0 . 5 V DD when CLK goes from HIGH LOW closed open transparent to LOW, that could make the NOR gates in the slave go HIGH open closed opaque metastable.
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