ENEL 353 F13 Section 02 Slides for Lecture 12 slide 2/19 ENEL 353 F13 Section 02 Slides for Lecture 12 slide 3/19 Previous Lecture Today’s Lecture Slides for Lecture 12 ENEL 353: Digital Circuits — Fall 2013 Term A little more about drawing schematics. (Related reading in Harris & Harris: Sections 2.4.) Theorems T11, T11 ′ , T12, T12 ′ . Steve Norman, PhD, PEng The concept of a minimal SOP expression. (Related reading: Discussion of T12 and T12 ′ : De Morgan’s Theorem. Section 2.3.5.) Electrical & Computer Engineering Using theorems to simplify equations. Schulich School of Engineering Multilevel combinational logic. (Related reading: Section 2.5.) University of Calgary Going from logic equations to circuit designs. We’ll just get started on unknown/illegal (X) and 4 October, 2013 floating/high-impedance (Z) values in combinational logic. (Related reading: Section 2.6.) slide 4/19 slide 5/19 slide 6/19 ENEL 353 F13 Section 02 Slides for Lecture 12 ENEL 353 F13 Section 02 Slides for Lecture 12 ENEL 353 F13 Section 02 Slides for Lecture 12 Schematics: Guidelines for directions of Example schematic, showing elements processing Minimal SOP expressions information flow through circuit elements information left-to-right and top-to-bottom (This is a quick step back to textbook Section 2.3.5, to help with Problem Set 2.) A B C Please follow these guidelines: A minimal sum-of-products expression for a function, as you might guess, is in some sense a “simplest possible SOP ◮ Left-to-right flow of information through circuit elements A B C expression” for that function. is best. minterm: ABC ◮ Top-to-bottom flow through elements is second-best. Here is the precise definition: minterm: ABC ◮ Bottom-to-top flow through elements should be avoided if ◮ Among all possible SOP expressions for F , none have possible but sometimes helps to keep schematics clear fewer products than a minimal SOP expression. minterm: ABC and compact. ◮ Among all the possible SOP expressions for F that have ◮ Right-to-left flow through elements is worst, but, the same number of products as a minimal SOP nevertheless, sometimes helps to keep schematics clear expression, none use fewer literals. Y and compact. Image is Figure 2.23 from Harris D. M. and Harris S. L., Digital Design Note that a literal counts each time that it is used, so, for example, A ¯ and Computer Architecture, 2nd ed. , c � 2013, Elsevier, Inc. B + AC has four literals, not three. ENEL 353 F13 Section 02 Slides for Lecture 12 slide 7/19 ENEL 353 F13 Section 02 Slides for Lecture 12 slide 8/19 ENEL 353 F13 Section 02 Slides for Lecture 12 slide 9/19 Minimal SOP expressions, continued Two-level combinational logic Multilevel combinational logic A B C Here are three SOP expressions for a function: first level Circuits designed to Two-level SOP-based designs often work well, but if they do F = A ¯ B ¯ C + A ¯ BC + ABC (1) implement SOP not, designs with three or more levels of gates may be better = A ¯ expressions using AND B + ABC (2) choices. gates and OR gates are = A ¯ B + AC (3) Textbook Section 2.5.1 give examples of cases where non-SOP called two-level logic . designs work much better than two-level SOP-based designs. (NOT gates needed to Let’s explain why (1) and (2) do not satisfy the definition of a provide complements Textbook Section 2.5.2 describes a technique called “bubble minimal SOP expression for F. of input variables don’t pushing” that can be very helpful in understanding multilevel It turns out to be true that (3) is minimal, but we don’t have count as levels in this designs that use NAND and NOR gates. second level a way to prove that yet. We’ll return to that issue when we definition.) get to Karnaugh maps . Y
ENEL 353 F13 Section 02 Slides for Lecture 12 slide 10/19 ENEL 353 F13 Section 02 Slides for Lecture 12 slide 11/19 ENEL 353 F13 Section 02 Slides for Lecture 12 slide 12/19 Hardware reduction via multilevel design Hardware reduction via multilevel design, continued Alternative interpretations of NAND and NOR Textbook reference: Section 2.5.1. Remember that De Morgan’s Theorem says things such as Textbook reference: Section 2.5.1. ABC = ¯ A + ¯ B + ¯ C and A + B + C + D = ¯ A ¯ B ¯ C ¯ Continuing to follow the textbook presentation, consider the D . Definition of N -input XOR: problem of implementing an 8-input XOR function. Below are That results in alternate symbols for NAND and NOR gates, � 1 two choices. (Of course there are other choices as well.) if the number of 1 inputs is odd for example: XOR( A 1 , A 2 , . . . , A N ) = 0 if the number of 1 inputs is even Three-level “tree” of . . . can be thought of as . . . seven 2-input XOR Page 70 in the textbook shows that the 3-input XOR (which Two-level, SOP-based: gates: happens to be the sum function of a 1-bit full adder) requires four 3-input AND gates and a 4-input OR gate to implement ◮ 128 8-input AND . . . can be thought of as . . . the minimal SOP expression. gates! The textbook goes on to show that 3-input XOR can be ◮ One 128-input OR You can think of moving bubbles through gates and implemented using only two 2-input XOR gates—a significant gate! interchanging AND with OR as bubble pushing . Bubble improvement over the SOP-based circuit. pushing does not change the behaviour of a gate. slide 13/19 slide 14/19 slide 15/19 ENEL 353 F13 Section 02 Slides for Lecture 12 ENEL 353 F13 Section 02 Slides for Lecture 12 ENEL 353 F13 Section 02 Slides for Lecture 12 Bubble pushing for analysis of circuits with NAND Bubble pushing for analysis of circuits with NAND Illegal (X) and Floating (Z) Values in Logic Circuits and NOR gates and NOR gates—example A Textbook reference: Section 2.6. Textbook reference: Section 2.5.2. In pure Boolean algebra, a variable can have only one of two Y B values: 0 or 1. This is a procedure to allow interpretation of logic in terms of C ORs and ANDs rather than NANDs and NORs . . . However, in modeling logic circuits, it’s sometimes useful to ◮ Start at the output and work towards the inputs. have a more complex model. This model says that a node in a D circuit can have one of four values: 0, 1, X or Z. ◮ If the gate that drives the overall output is NAND or Let’s use bubble pushing to express Y in terms of AND and NOR, push its bubble to its inputs. Before getting into the details of what X and Z values mean, OR operations, perhaps with NOT applied to some of the ◮ For all the other gates, push bubbles as necessary so that it’s helpful to understand a very approximate model of how inputs. each internal wire has either no bubbles or cancelling logic gates work . . . bubbles at both ends . There is a similar example starting near the bottom of page 71 in the textbook. ENEL 353 F13 Section 02 Slides for Lecture 12 slide 16/19 ENEL 353 F13 Section 02 Slides for Lecture 12 slide 17/19 ENEL 353 F13 Section 02 Slides for Lecture 12 slide 18/19 Basic structure of a CMOS logic gate Simple model for a CMOS gate with LOW output Simple model for a CMOS gate with HIGH output The pull-up and pull-down networks are collections of MOS This should give you an idea why the voltage on the output is This should give you an idea why the voltage on the output is transistors . (Details of MOS transistors are a major topic in near 0 V . . . near V DD . . . courses later in the ENEL degree program.) V DD V DD V DD pull-up network is OFF SMALL resistance pull-up network is ON pull-up . . . near INFINITE resistance network when output should be 1 . . . SMALL resistance inputs output inputs output inputs output pull-down pull-down network is ON SMALL resistance pull-down network is OFF network . . . SMALL resistance when output should be 0 . . . near INFINITE resistance GND GND GND In normal operation one of the pull-up/pull-down networks is ON The actual behaviour of the transistors inside the pull-up and Again, real circuit behaviour is not quite this simple. and the other one is OFF. Which network is ON and which is pull-down networks is more complicated than this model suggests! OFF depends on the bit pattern on the input wires.
ENEL 353 F13 Section 02 Slides for Lecture 12 slide 19/19 Upcoming topics Completion of material on X and Z values at nodes of logic circuits. Karnaugh maps (also known as K-maps ). Related reading in Harris & Harris: Sections 2.6 and 2.7
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