cmos switched capacitor circuits recent advances in bio
play

CMOS Switched-Capacitor Circuits: Recent Advances in Bio-Medical and - PowerPoint PPT Presentation

CMOS Switched-Capacitor Circuits: Recent Advances in Bio-Medical and RF Applications David J. Allstot Univ. of Washington Dept. of Electrical Engineering Seattle, WA 98195-2500 ASU August 17, 2011 Motivation 2010: 4.6 B subscribers


  1. CMOS Switched-Capacitor Circuits: Recent Advances in Bio-Medical and RF Applications David J. Allstot Univ. of Washington Dept. of Electrical Engineering Seattle, WA 98195-2500 ASU August 17, 2011

  2. Motivation  2010: 4.6 B subscribers  2012: 1 B WiFi  US mobile phones:  Use yearly energy of 638,000 US Homes  Emit 6K tons CO 2  Demand increases with newer data PA phones  PA is dominant Metropolitan energy hog Seattle Area 2 ASU August 17, 2011

  3. CMOS PA Trends: P out J.S. Walling, S.S. Taylor and D.J. Allstot, “A class-G supply modulator and class-E PA in 130 nm CMOS,” IEEE JSSC , pp. 2339-2347, Sept. 2009. S.-M. Yoo, J.S. Walling, E.C. Woo and D.J. Allstot, “A switched-capacitor power amplifier for EER/Polar transmitters,” IEEE ISSCC Dig. Tech. Papers , pp. 428-429, 2011. 3 ASU August 17, 2011

  4. CMOS PA Trends: PAE 4 ASU August 17, 2011

  5. Outline  Challenges in CMOS RF PA Design  Switched-Capacitor PA Solution  Analog-domain Compressed Sensing for Bio-signal Acquisition 5 ASU August 17, 2011

  6. Challenge: Max Power Out  V DD Scaling V DD   2  V V DD SAT = P out 2 R L  Impedance Transformation  45 nm CMOS 1W, V DD = 1.0 V Linear PAs V out V SAT = 0.2 V 1 : n  R L R opt R opt 0.3  = = 50  R L /n 2  Parasitic R Limit) 6 ASU August 17, 2011

  7. Challenge: Efficiency  Linear Power Amplifiers P  = L – AM Signals (i.e., non- P Constant Envelope) DC 2   V – Class-A:  = 0.5  out    V   DD 2    V – Class-B:  = 4   out   V   – Class-AB DD – Class-C: Peak  = 100% @ P out = 0 (Attractive for Body Area Networks) 7 ASU August 17, 2011

  8. Challenge: Efficiency  Switching Power Class-E PA Amplifiers Impedance Transformer & Wave-Shaping Network – PM and FM Signals (i.e., Constant Envelope)  Class D, E, F, etc.  Zero-V Switching = = 0 P v i – Rise in v D delayed DC D D until switch OFF – v D = 0 @ switch ON ON  dv D / dt = 0 @ switch OFF OFF  Ideal  = 100% 8 ASU August 17, 2011

  9. Spectral vs. Energy Efficiency QAM FM 64-QAM 25 25 100 20 20 80 Ocurrences (%) Ocurrences (%) Ocurrences (%) 15 15 60 10 10 40 5 5 20 0 0 0 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 Normalized Envelope (V) Normalized Envelope (V) Normalized Envelope (V) 9 ASU August 17, 2011

  10. Linearization Techniques  Feedforward  Feedback  LINC – Linear Amp with Nonlinear Components  EER – Envelope Elimination and Restoration – Can use highly-efficient switching PA; e.g., Class-E – P out  V DD for Switching PA – Split signal into envelope (A) & phase (  ) paths – Improved overall efficiency – Distortion from delay mismatches in A &  paths 10 ASU August 17, 2011

  11. Kahn EER Technique (1952) A Original Kahn  Modern Kahn  Polar conversion in DSP using CORDIC Algorithm  DAC and supply modulator needed 11 ASU August 17, 2011

  12. LDO Modulator & Efficiency  LDO Characteristics – V out ≈ ENV in  – P v i out out out  i out – P v i DD out DC    – P / P v / V LDO = Low-dropout Reg. out DC out DD  Overall efficiency is product of supply modulator and PA LDO efficiencies  Increased  over Linear PA 12 ASU August 17, 2011

  13. Class-G: Spectral vs. Energy Efficiency  Small envelope: Use Vdd/x  Large envelope: Use Vdd Dual-Supply Modulator  Extend to more than two power supplies? Class-H? 13 ASU August 17, 2011

  14. Class-G: Spectral vs. Energy Efficiency 100 10  Overall efficiency Class-E is product of Class-G 80 8 class-G modulator Drain Efficiency (%) and class-E PA Probability (%) 60 6 Avg. efficiencies Class-G Class-B 40 4  Ideally 5X higher average  than 20 2 Avg. Class-B OFDM PDF linear PA for this 0 10 probability density 0 0 0.2 0.2 0.4 0.4 0.6 0.6 0.8 0.8 1 V out (V) function 14 ASU August 17, 2011

  15. Class-E PA and Driver  Interstage tuning inductors reduce driver power  Driver taper of 2 – custom stages 15 ASU August 17, 2011

  16. 130nm Class-G PA 16 ASU August 17, 2011

  17. Class-G Static Measurements 1000 80 80 8 Class G PAE 64QAM OFDM PDF Theory Avg PAE 800 64 Meas. Avg PAE Output Power (mW) 60 6 Probability (%) Efficiency (%) 600 48 PAE (%) 40 4 400 32 20 2 200 16 0 0 0 0 0 0 0.2 0.2 0.4 0.4 0.6 0.6 0.8 0.8 1 1 0 0 0.2 0.2 0.4 0.4 0.6 0.6 0.8 0.8 1 1 Input Envelope 2 (V 2 ) Normalized Envelope (V) Freq = 2 GHz 64 QAM OFDM Symbol Period = 4  s  Theoretical avg. PAE = 24%  Measured avg. PAE = 22% 17 ASU August 17, 2011

  18. Class-G Dynamic Measurement 0 Norm. Output Power (dB) -20 -40 -60 -80 -80 -60 -40 -20 0 20 40 60 80 Frequency Offset (MHz) Freq = 2 GHz rms EVM = 2.5% 18 ASU August 17, 2011

  19. Digitally-Modulated PA PA based on digital modulation Unit current cells [Kavousian, et al., ISSCC 2007 ] [Presti, et al., JSSC 2009] • DAC, supply modulator functions combined – No supply modulator: Higher efficiency and smaller area • Multiple unit current-cell-based PAs as DAC 19 ASU August 17, 2011

  20. Current-Cell-Based PA Nonlinear V OUT V OUT Saturated Linear Input Code • Accuracy / Efficiency Tradeoff • Accurate current cell requires high r out – Cascode more headroom: Lower efficiency • Extra resolution required for predistortion P P • Efficiency: OUT OUT     P Ideal OUT P V DC OUT 20 ASU August 17, 2011

  21. Switched-Capacitor Basics (a) Precharge and Reset (b) Charge Redistribution w/o precharge • Energy is lost w/ precharge and reset • No energy lost in charge redistribution w/o precharge 21 ASU August 17, 2011

  22. SCPA in Polar Transmitter 22 ASU August 17, 2011

  23. Basic SCPA Concept • SC technique can be used for voltage generation • Easy to split into capacitor bank (small area & loss) – Resonant frequency maintained (Constant C) Constant envelope Good efficiency 23 ASU August 17, 2011

  24. Switched-Capacitor PA Constant Capacitance • Capacitor can be arrayed – Single capacitor can be split into many – Each capacitor is switched to VDD or GND – Constant resonant frequency – RF Switched-Capacitor DAC 24 ASU August 17, 2011

  25. Thevenin Equivalent Circuit Constant Capacitance = C C C U =C 1 =C 2 =C n =C N = N • Digitally-controlled output voltage • Constant top-plate capacitance vs. the number of switched capacitors 25 ASU August 17, 2011

  26. Output Power P out delivered to R OUT • V OUT  n/N • P OUT  (n/N) 2 • 4/  for 1 st harmonic component n    2   1 4 2 2 n V  V OUT =   P OUT = V DD  DD    2   2 N N R 26 ASU August 17, 2011

  27. Power Dissipated in SC • Charging & discharging with switch → CV 2 f dynamic power • Assume fast t r ,t f with constant current through L • Effective switched capacitance varies with envelope code 27 ASU August 17, 2011

  28. Ideal Efficiency • Higher efficiency with higher Q Loaded • Higher Q Loaded : - Smaller Capacitance - Less CV 2 f dynamic power - Efficiency tradeoff due to L & switch 2 4 n P    OUT    2 fL 1  n ( N n )   P P  Q Loaded 2 OUT SC 4 n  R 2 fCR Q Loaded 28 ASU August 17, 2011

  29. Practical Efficiency Ideal  vs. Practical  P   OUT  Ideal P P SC OUT Practical  (%)     Ideal  (%) P   OUT     P P P P P SC OUT SWC DR CLOCK • Practical implementation: − Lossy inductor:  →  Normalized P OUT (dBm) →  − SW parasitic R:  Benefit − SW parasitic C: 2 P ( n / N ) C V f SWC SW DD from  − Switch driver: 2 P ( n / N ) C V f DR DR DD scaling  − Clock distribution: 2 P C V f CLOCK CLOCK DD 29 ASU August 17, 2011

  30. CMOS Switch as Voltage Source AM-AM CB AM-PM VDD Voltage (CB) n/N 0.25 0.5 0.75 0 1 time 0 1/fs • Faster switch improves both AM-AM and AM-PM distortion performance (e.g., better with CMOS scaling) 30 ASU August 17, 2011

  31. 6-bit Switched-Capacitor Array • Split into 4-bit unary and 2-bit binary arrays • Additional bits possible – More unary/binary bits or C-2C ladder • Unit-cell switch and switch-driver 31 ASU August 17, 2011

  32. Switch Implementation • Cascode  More output power with same R out • Total supply voltage of 2VDD • All thin-gate devices • Separate driver voltage ranges for NMOS & PMOS 32 ASU August 17, 2011

  33. Switched-Capacitor PA Schematic Bandpass Matching Network C= 8.2pF 33 ASU August 17, 2011

  34. Chip Microphotograph • 90 nm RF LP CMOS process (MIM cap and UTM) 1430  m Capacitor Array Switch, 730  m Drivers, Output Matching Network Logic & Bypass Capacitor 34 ASU August 17, 2011

  35. PA Measurement: P out & PAE • Fewer P driver at backoff • 6-bit implementation •  Peak = 45% 35 ASU August 17, 2011

  36. AM-AM & AM-PM / P out vs. Freq. • Different impedance seen • Peak P out ≥ 24dBm from source depending • Peak  ≥ 45% on input code • Scaling friendly 36 ASU August 17, 2011

Recommend


More recommend