I nGaAs MOSFETs for CMOS: Recent Advances in Process Technology J. - PowerPoint PPT Presentation

I nGaAs MOSFETs for CMOS: Recent Advances in Process Technology J. A. del Alamo, D. Antoniadis, A. Guo, D.-H. Kim 1 , T.-W. Kim 2 , J. Lin, W. Lu, A. Vardi and X. Zhao Microsystems Technology Laboratories, MIT 1 Global Foundries 2 Sematech International Electron Devices Meeting 2013 Washington D.C., December 9, 2013 Acknowledgements : • Sponsors: Intel, FCRP-MSD, Sematech, NSF, SMA, MIT-Technion • Labs at MIT: MTL, NSL, SEBL 1

I nGaAs High Electron Mobility Transistors g m =2.7 mS/ μ m Kim, IEDM 2011 InGaAs InAlAs channel barrier Main attractions of InGaAs: • μ e = 6,000 - 30,000 cm 2 /V.s @ 300K • v inj = 2.5 - 3.7x10 7 cm/s @ 300 K 2

I nGaAs MOSFETs g m =2.7 mS/ μ m Lin, IEDM 2013 * InGaAs High-K channel oxide *inversion-mode Extraordinary recent progress of InGaAs MOSFETs 3

Technology issue # 1: MOS gate stack Challenge: metal/high-K oxide gate stack – Fabricated through ex-situ process – Very thin barrier (EOT ~ 0.5 nm) – Low gate leakage (I G <1 A/cm 2 at V GS =0.5 V) – Low D it (<3x10 12 eV -1 .cm -2 in top ~0.3 eV of bandgap and inside CB) – Reliable high-K dielectric n + n + 4

I nterface quality: Al 2 O 3 / I nGaAs vs. Al 2 O 3 / Si Al 2 O 3 /Si Al 2 O 3 /InGaAs E v E c E v E c Brammertz, APL 2009 Werner, JAP 2011 Close to E c , Al 2 O 3 /InGaAs comparable D it to Al 2 O 3 /Si interface 5

Buried-channel vs. surface channel? Classic trade-off: – Surface channel: high scalability but low mobility (µ e <2,000 cm 2 /V.s) – Buried channel: high mobility but high EOT and t barr ↓  µ e ↓ 12 nm Al 2 O 3 InP good choice for barrier: Urabe, ME 2011  wide E g , lattice matched to In 0.53 Ga 0.47 As 6

HfO 2 vs. Al 2 O 3 in buried-channel MOSFETs 500 °C PDA L g = 150 nm -4 10 V ds = 50 mV -1 ) -5 10 -2 eV Al 2 O 3 100 I d (A/  m) S~85 mV/dec -6 12 cm 10 HfO 2 -7 10 D it (x10 10 HfO 2 (2 nm) -8 10 E V E C InP Al 2 O 3 /HfO 2 (0.4/2 nm) -9 1 10 -0.8 -0.4 0.0 0.4 0.8 -0.4 -0.2 0.0 0.2 0.4 E-E i (eV ) V gs (V) Galatage - UT Dallas, 2012 HfO 2 (2 nm) directly on InP (1 nm): EOT~0.8 nm • Low D it close to E c EOT~1 nm • Steep subthreshold swing • Low I off (nA/ μ m range) Lin, IEDM 2012 7

HfO 2 in surface-channel MOSFETs EOT~0.5 nm EOT~0.8 nm Lin, IEDM 2013 HfO 2 (2.5 nm) directly on InGaAs: • Comparable S as buried-channel device D it ~2x10 12 • EOT ↓  I d ↑ eV -1 .cm -2 • Low ALD temperature key Suzuki, JAP 2012 8

Pristine interface for high MOS quality Semiconductor surface exposed SiO 2 immediately before MOS formation Mo n + cap n+ cap i-InP Channel  -Si Barrier: InP (1 nm) + Al 2 O 3 (0.4 nm) + HfO 2 (2 nm) Lin, IEDM 2012 • S = 69 mV/dec at V DS = 50 mV • Close to lowest S reported in any III-V MOSFET: 66 mV/dec [Radosavljevic, IEDM 2011] 9

Technology issue # 2: ohmic contacts Challenge: nanometer-scale ohmic contacts with low R c – Tiny (L c < 30 nm) – Low contact resistance (R c < 50 Ω .µm) – Self-aligned to gate (L side < 10 nm) 10

New “nano-TLM” test structure to characterize short contacts � || � � ��� � csch � �� � �� � � � � ��� � � � � ��� � csch � coth 2� �� � �� � �� 2� � Lu, EDL (submitted) Decouples impact of metal resistance on short contacts 11

Contact-first process for Mo-I nGaAs ohmic contacts Fabrication process: Surface cleaning Mo deposition E-beam lithography Mo RIE Mesa isolation Pad metallization Contact anneal Lu, EDL (submitted) • Achieved contacts with length down to 19 nm • Contact-first process preserves high-quality interface 12

Nanometer-scale Mo-I nGaAs contacts Mo on n + -In 0.53 Ga 0.47 As: Dormaier JVSTB 2012 Singisetti APL 2008 Baraskar JAP 2013 Crook APL 2007 Lin JAP 2013 Lu, EDL (submitted) 6.6 Ω . μ m • R c blows up for very small contacts with L c < L t = 113 nm • R c ~ 40 Ω . μ m for L c ~ 20 nm Average  c = 0.69  .  m 2 • • Contacts thermally stable up to 400 o C 13

Ni-I nGaAs ohmic contact Subramanian, JES 2012 Oxland, EDL 2012 • Ni diffused into InGaAs at 250 o C Kim, IEDM 2010 • Ni-InGaAs formed • Unreacted Ni removed using HCl-based selective etchant R c ~ 50  .  m demonstrated [Kim VLSI Tech 2013] • 14

Technology issue # 3: self-aligned MOSFET architectures Challenge: ohmic contacts very closely spaced from gate – Design of access region – Must maintain high-quality MOS interface and low R c Gate-first process : Gate-first process : Gate-last process : “silicided” S/D regrown S/D recessed S/D Hill, IEDM 2010 Egard, IEDM 2011 Radosavljevic, IEDM 2009 Kim, VLSI Tech 2013 Zhou, IEDM 2012 Lin, IEDM 2012 Lee, VLSI Tech 2013 15

Gate-last self-aligned I nGaAs MOSFETs • Ohmic contact first (Mo) • Extensive RIE (F-based) • Interface exposed immediately before gate stack formation • Process designed to be compatible with Si fab • RIE damage annealed at 340 o C: Lin, IEDM 2012 16

Gate-last self-aligned I nGaAs MOSFETs Lin, IEDM 2012 Lin, IEDM 2013 W Mo L g =50 nm L side • Buried-channel (EOT~0.8 nm) • Surface-channel (EOT~0.5 nm) • Wet semiconductor etch • Dry semiconductor etch + digital etch of cap • L side ~ 30 nm • L side ~ 5 nm 17

I mpact of L side L g = 70 nm Lin, IEDM 2013 500 L side ↓ 400 I on (  A/  m)  g m ↑ 300  S ↑ 200  I on at fixed I off ↓ I off =100 nA/  m, V dd =0.5 V 100  GIDL ↑ 0 50 100 150 200 L g (nm) 18

Technology issue # 4: Tri-gate MOSFET Challenge: acceptable I ON and SCE on a small-footprint – Planar design does not provide enough “electrostatic integrity” – Need tighter channel control through 3D device design Wu, IEDM 2009 Radosavljevic, IEDM 2010 Chin, EDL 2011 Radosavljevic, IEDM 2011 Planar MOSFET Tri-gate MOSFET 19

Fin formation Direct fin growth by Fin etch by Aspect Ratio Trapping RIE + digital etch 20 nm • BCl 3 /SiCl 4 /Ar RIE chemistry • Digital etch: self-limiting (2 nm/cycle) • Some defects reach surface • No notching in heterostructures • Inter-diffusion of dopant species Fiorenza, ECST 2010 Zhao, IEDM 2013 Waldron, ECST 2012 20

Mo contacts to fin • Mo-first process • Mo used as mask for fin etch Mo Mo sidewall contacts • With top Mo contact: Mo − R c ~ 7 Ω . μ m • With sidewall contact: 100 nm − R c ~ 12 Ω . μ m Mo on sidewalls 21

Fin sidewall MOS Double-gate sidewall MOSFET to study sidewall MOS quality Mo SiO 2 25 nm Al 2 O 3 W f =30 nm V GS =0.5 V 10 1 10 I D [  A  m] I D [  A/  m] At sidewall: 0.1 W f =35 nm D it ~ 1.4x10 13 eV -1 .cm -2 0.01 V GS =0.3 V 5 1E-3 W f =30 nm V GS =-0.1 V V GS =0.1 V 1E-4 W f =25 nm 0 0.0 0.1 0.2 0.3 0.4 0.5 -1 0 1 2 V GS [V] V GS [V] 22

Conclusions • Remarkable recent progress in InGaAs MOSFETs – g m (MOSFET) = g m (HEMT) – R on (MOSFET) < R on (HEMT) Compact, self-aligned devices; link to be engineered to Very low R c balance performance and SCE contacts at close to target length Good quality MOS stack close to target EOT • Many issues to investigate: – Tri-gate technology, integration with p-MOSFETs on Si, reliability 23