A CMOS-Compatible Fabrication Process for Scaled Self-Aligned I - PowerPoint PPT Presentation

A CMOS-Compatible Fabrication Process for Scaled Self-Aligned I nGaAs MOSFETs Jianqiang Lin Dimitri Antoniadis and Jesús del Alamo Microsystems Technology Laboratories, MIT CS MANTECH, May 18-21, 2015 Acknowledgements: DTRA NSF E3S STC MIT SMART program 1

Motivation for III-V CMOS • Superior electron transport properties for III-Vs V inj : source injection velocity • III-V’s: promising to extend Moore’s Law • Focus of this talk: InGaAs MOSFET fabrication technology 4

Self-aligned recessed-gate QW-MOSFET HEMTs Considerations for III-V MOSFETs • Gate insulator – thin with low leakage, low D it • High-level self-alignment – ohmic metal, access region, gate 2  m • CMOS compatibility [Kim IEDM 2011] – free of wet-etch, lift-off and Au Proposed MOSFET structure: 3

Process overview CF 4 , SF 6 anisotropic RIE Mo/W ohmic contact CF 4 +O 2 isotropic RIE Resist SiO 2 W/Mo n + cap InP InGaAs/InAs  -Si InAlAs [Lin, APEX 2012] [Lin, IEDM 2013] [Waldron, IEDM 2007] III-V recess Gate stack Via and pad Via Mo HfO 2 [Lin, IEDM 2012-2014] 4

Details of contact and III-V recess processes CF 4 , SF 6 anisotropic RIE Mo/W ohmic contact CF 4 +O 2 isotropic RIE Resist SiO 2 W/Mo n + cap InP InGaAs/InAs  -Si InAlAs [Lin, APEX 2012] [Lin, IEDM 2013] [Waldron, IEDM 2007] III-V recess Gate stack Via and pad Via Mo HfO 2 [Lin, IEDM 2012-2014] 5

W barrier for undercut immunity Goal: to reduce device footprint and gate pitch size Oxidized Mo SiO 2 Mo [Lin, IEDM 2012] (a) 20 nm [Lin, IEDM 2013] [Lin, IEDM 2012] 6

Problems with wet etch gate recess • Isotropic wet etch → large lateral extent – Large footprint – Ungated and uncapped access regions → access resistance ↑ 7

New III-V recess technology: Precise channel thickness (t c ) control Cl 2 anisotropic RIE • Anisotropic SiO 2 W/Mo n + InGaAs/InP InP InGaAs/InAs  -Si InAlAs 8

III-V dry etch: surface roughness Selected chemistry Cl 2 :N 2 As-grown Selected recipe Key parameters:  Bias  Pressure  Gas ratio (Cl 2 :N 2 )  Gas chemistry Not selected recipes 9 [Zhao EDL 2014]

III-V dry etch: trenching BCl 3 -chemistry [Zhao IEDM 2014] Cl 2 :N 2 -chemistry 10 Low bias High bias

New III-V recess technology: Precise channel thickness (t c ) control Cl 2 anisotropic RIE • Anisotropic SiO 2 • Accurate depth control W/Mo n + InGaAs/InP InP InGaAs/InAs  -Si InAlAs 1 nm/cyc O 2 Plasma H 2 SO 4 Digital Etch (DE) [Lin, EDL 2014] 11

New III-V recess technology: Precise channel thickness (t c ) control Cl 2 anisotropic RIE • Anisotropic SiO 2 • Accurate depth control W/Mo n + InGaAs/InP • Accurate and fast calibration InP InGaAs/InAs  -Si InAlAs 1 nm/cyc O 2 Plasma H 2 SO 4 Digital Etch (DE) [Lin, EDL 2014] 12

Precise channel thickness (t c ) control 1 nm depth control t c = t c = 800 Device scaling study DIBL (mV/V) 600 t c =12 nm  ON-state: I ON , g m , R SD 400  OFF-state: S, DIBL, V t roll-off 200 3 nm [Lin, TED submitted] 0 0.01 0.1 1 10 13 L g (  m)

Typical long-channel characteristics -3 10 -4 10 -5 10 I d (A/  m) -6 10 83 mV/dec -7 10 -8 L g =120 nm 10 V ds =0.05 and 0.5 V -9 10 -0.2 0.0 0.2 0.4 V gs (V) • Steep S at low V ds → Low D it • J g < 10 -2 A/cm 2 at EOT~0.5 nm → gate leakage suppression (typical HEMT: J g >100 A/cm 2 ) 14

Scalability and performance Scalability Performance [Lin, IEDM 2014] 3.1 mS/  m 1.0 V gs -V t = 0.5 V L g =20 nm MIT MOSFETs R on =224  m 0.8 0.4 V I d (mA/  m) 0.6 Ref: del Alamo 0.4 ESSDERC 2013 (updated) 0.2 0.0 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) 15

Conclusions • Scalable self-aligned InGaAs MOSFETs – CMOS manufacturability, performance, scalability • Bilayer ohmic contact for footprint scaling • III-V recess – III-V dry etch: smooth surface and no trenching – Digital etch: accurate depth control • InGaAs MOSFET performance analysis – Steep subthreshold swing: low D it – Gate leakage suppression – Record transconductance achieved – Working L g =20 nm InGaAs MOSFETs 16