A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs - PowerPoint PPT Presentation

A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs Alon Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao and Jesús A. del Alamo Microsystems Technology Laboratories, MIT May 23, 2017 Sponsors: DTRA (HDTRA 1‐14‐1‐0057), NSF E3S STC (grant #0939514) Lam Research

Outline • Motivation • Process technology • Electrical characteristics • Late news • Conclusions 2

Historical evolution: InGaAs High-Electron Mobility Transistor High-Electron Mobility Transistor Transconductance (g m =dI D /dV GS ): • Superior electron transport properties in InGaAs 3

InGaAs MOSFETs vs. HEMTs High-Electron Mobility Transistor Transconductance (g m =dI D /dV GS ): Metal-Oxide-Semiconductor Field-Effect Transistor • Superior electron transport properties in InGaAs 4

InGaAs MOSFETs vs. HEMTs High-Electron Mobility Transistor Transconductance (g m =dI D /dV GS ): g m =3.45 mS/μm Lin, EDL 2016 Metal-Oxide-Semiconductor Field-Effect Transistor What happened here? • Superior electron transport properties in InGaAs • InGaAs planar MOSFET performance exceeds that of High Electron 5 Mobility Transistors (HEMT)

Atomic Layer Deposition (ALD) of gate oxide ALD eliminates residual native oxides that pin Fermi level  “Self cleaning” Huang, APL 2005 Clean, smooth interface without native oxides • First with Al 2 O 3 , then with other high-K dielectrics • First in GaAs, then in other III-Vs 6

InGaAs planar Quantum-Well MOSFETs - short-channel effects 300 V DS =0.5 V 250 S min (mV/dec) t c =12 mn 200 150 100 7 mn 0.01 0.1 1 10 L g (  m) Lin, IEDM 2014 • Short‐channel effects limit scaling to L g ~ 40 nm • 3D transistors required for further scaling 7

FinFETs Intel Si Trigate MOSFETs • FinFETs used in state‐of‐the‐art Si CMOS • Good balance of SCE and high ON current per footprint 8

InGaAs FinFETs W f ~25 nm W f ~30 nm W f ~50 nm W f ~50 nm Thathachary, VLSI 2015 Zota, IEDM 2016 Waldron, VLSI 2014 W f ~15 nm Kim, IEDM 2013 Radosavljevic ,IEDM 2011 Djara, VLSI 2015 Kim, TED 2014 • Demonstrations to date: W f ≥ 15 nm, AR c ≤ 2 9

Goal: Sub-10 nm W f Self-aligned III-V FinFETs High ‐K HSQ SiO 2 L g W/Mo cap W f channel H c AR c = H c /W f InAlAs • Deeply scaled W f , L g and EOT • High channel aspect ratio (AR c ) • Self-aligned contacts • CMOS-compatible processes and materials in front- end 10

From InGaAs HEMT to finFET InGaAs HEMT del Alamo, CS MANTECH 2011 50nm • Contact first InGaAs Planar MOSFET • Gate recess Lin, CS MANTECH 2015 InGaAs FinFET 100 nm 11 Vardi, CSMANTECH 2017

Fin definition: RIE + Digital etch 170 nm 8 nm 100 nm 30 nm • BCl 3 /SiCl 4 /Ar RIE: smooth, vertical sidewalls and high aspect ratio (>10) • Digital etch (DE) : self‐limiting O 2 plasma oxidation + H 2 SO 4 oxide removal Zhao, EDL 2014 12 Vardi, VLSI 2016

Device fabrication 30 nm In 0.53 Ga 0.47 As, Si doped 3e19 cm ‐3 4 nm InP stopper 40 nm In 0.53 Ga 0.47 As, undoped • Highly doped cap 5 nm • 40 nm thick channel layer Si  ‐Doping: 4e12 cm ‐2 • Delta doping underneath 400 nm In 0.52 Al 0.48 As buffer InP semi insulating substrate 13

Device fabrication W f direction L g direction Sputtered W/Mo contact o CVD SiO 2 hard mask SiO 2 o W/Mo cap channel InAlAs 14

Device fabrication L g direction Sputtered W/Mo contact W f direction o CVD SiO 2 hard mask o SiO 2 35 nm L g Gate lithography o W/Mo Gate recess (Dry): o cap SiO 2 /W/Mo SiO 2 channel Active area definition o W/Mo InAlAs 15

Device fabrication L g direction Sputtered W/Mo contact W f direction o CVD SiO 2 hard mask o SiO 2 35 nm L g Gate lithography o W/Mo Gate recess (Dry): o cap SiO 2 /W/Mo SiO 2 channel Active area definition o W/Mo Gate recess (Wet): Cap o etch InAlAs L g 60 nm SiO 2 W/Mo InP InGaAs 20 nm 16

Device fabrication HSQ Sputtered Mo contact o SiO 2 CVD SiO 2 hard mask o W/Mo Gate lithography o cap Gate recess (Dry): o channel H c SiO 2 /W/Mo H f Active area definition o Buffer Gate recess (Wet): Cap 100 nm o etch Fin Lithography o Fin etch o 17

Device fabrication HSQ SiO 2 Sputtered W/Mo contact o CVD SiO 2 hard mask W/Mo o cap Gate lithography o Gate recess (Dry): channel o H c SiO 2 /W/Mo H f Active area definition o Buffer 100 nm Gate recess (Wet): Cap o etch Fin lithography o Fin etch o Mo Digital etching o High‐k/Mo ALD gate dielectric o HSQ deposition Mo gate sputtering 20 nm o • Double gate FinFET • HfO 2 , gate oxide EOT = 0.6 nm 18

Device fabrication Sputtered W/Mo contact o CVD SiO 2 hard mask o Gate lithography o Gate recess (Dry): o SiO 2 /W/Mo Active area definition o Gate recess (Wet): Cap o etch Via Fin Lithography o Fin etch o SiO 2 Digital etching o ALD gate dielectric o deposition Gate hat Mo gate sputtering o Gate head photo and o pattern • Fin pitch: 200 nm ILD1 deposition o Via opening o Pad formation • 10-50 fins/device o 19

Long-channel characteristics, W f =22 nm, L g =0.5 μ m HfO 2 , EOT = 0.6 nm 250 V GS =0 to 0.75 V V DS =0.5 V 10 -4 ΔV GS = 0.25 V 200 0.05 V I d [ A/ m] 10 -6 150 I d [A/ m] 68 mV/dec 10 -8 100 50 10 -10 0 0 0.1 0.2 0.3 0.4 0.5 10 -12 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 V DS [V] V GS [V] • S lin =68 mV/dec • Negligible DIBL • Good electrostatic control over dry etched sidewalls 20

Most aggressively scaled FinFET W f =7 nm, L g =30 nm, H c =40 nm (AR=5.7), EOT=0.6 nm: 1E-3 1E-4 V DS =500 mV 500 V GS =-0.5 to 0.75 V DS =50 mV 1E-5  V GS =0.25 V DIBL=90 mV/V I d [A/  m] 400 S sat =100 mV/dev 1E-6 I d [  A/  m] 300 1E-7 200 1E-8 100 1E-9 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 V GS [V] 0.0 0.1 0.2 0.3 0.4 0.5 g m max =900  S/  m V DS [V] 1000 800 Current normalized by 2xH c V DS =0.5 V g m [  S/  m] 600 At V DS =0.5 V: • 400 g m =900 µS/µm • R on =320 Ω.µm 200 • S sat =100 mV/dec 0 -0.4 -0.2 0.0 0.2 0.4 Vardi, EDL 2016 V GS [V] 21

L g and EOT scaling (W f ~20 nm) 250 A: Al 2 O 3 , EOT=2.8 nm 1600 B:Al 2 O 3 /HfO 2 , EOT=1 nm 1400 V DS =0.5 V 200 C: HfO 2 , EOT=0.6 nm 1200 W f  20-22 nm EOT  1000 S sat [mV/dec] 150 g m [  S/  m] 800 100 600 400 50 60 mV/dec 200 EOT  0 0 0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700 L g [nm] L g [nm] 0.4 0.2 EOT ↓  g m ↑, S min ↓, V T rolloff↓ 0.0 V T [V] -0.2 -0.4 Classical scaling with L g and EOT EOT  -0.6 0 100 200 300 400 500 600 700 L g [nm] 22

W f Scaling 1600 Gate leakage 150 1400 contamination 1200 1000 g m max [  S/  m] 100 S sat,min [mV/dec] 800 W f =22  nm 600  W f = 5 nm W f =7 nm 400 50 W f =12 nm 200 W f =17 nm 0  W f =22 nm 0 0 100 200 300 400 500 600 100 1000 L g [nm] L g [nm] Non-ideal W f scaling • D it (~5x10 12 cm -2 .eV -1 ) • W f ↓  g m ↓ • mobility degradation • line edge roughness?... • W f ↓  Constant S min 23

Benchmark g m normalized by gate periphery Best logic device both III‐V and Si Zota, IEDM 2016 W F H c MIT FinFETs: • AR c >1 • Sub‐10 nm W f 24

Benchmark g m normalized by fin width 20 W f 5.3 Si FinFETs (V DD =0.8 V) 15 4.3 g m /W f [mS/  m] 5.7 10 V DD =0.5 V 3.3 2.3 InGaAs FinFETs 1.8 1.8 5 1 0.18 0.66 0.32 0.23 1 0.57 0.63 0.6 0.8 0 0 20 40 60 W f [nm] For g m /W f : • Si > III‐V • MIT FinFETs > all other III‐V FInFETs 25

Post deadline results V GS = 0 to 0.5 V in 0.1 V steps 150 I d [ A/ m] 5nm 100 InGaAs 50 InP 0 0 0.1 0.2 0.3 0.4 0.5 V DS [V] 600 V DS = 500 mV 10 -4 V DS = 500 mV 500 50 mV EOT=0.8 nm 10 -6 g m [ S/ m] 400 I d [A/ m] L g =50 nm 300 65 mV/dec W f =5 nm 10 -8 200 50 mV H c =50 nm I g 10 -10 100 0 10 -12 -0.2 0 0.2 0.4 0.6 0.8 -0.2 0 0.2 0.4 0.6 0.8 V GS [V] 27 V GS [V]

Post deadline results - Benchmark • Record g m at W f =5 nm • Record AR • Improved SCE 28

Conclusions • Novel self-aligned gate-last FinFET: – Self-aligned gate to contact metals – CMOS process compatibility – Sub-10 nm fin width – AR c >1 – Double-gate FinFET • Excellent performance and short-channel effects in devices with L g =30 nm and W f =22 nm • Demonstrated subthreshold swing of 65 mV/dec in short channel devices • Still short of Si FinFETs performance 29

Thank you ! 30