Nanoscale III-V CMOS J. A. del Alamo Microsystems Technology - PowerPoint PPT Presentation

Nanoscale III-V CMOS J. A. del Alamo Microsystems Technology Laboratories Massachusetts Institute of Technology Compound Semiconductor Week 2016 Toyama, Japan; June 26-30, 2016 Acknowledgements: • Students and collaborators: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao • Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung • Labs at MIT: MTL, EBL

Moore’s Law at 50: the end in sight? 2

Moore’s Law Moore’s Law = exponential increase in transistor density 2016: Intel 22-core Xeon Broadwell-E5 7.2B transistors Intel microprocessors 3

Moore’s Law How far can Si support Moore’s Law? ? 4

Transistor scaling  Voltage scaling  Performance suffers Supply voltage: Transistor current density: Intel microprocessors Intel microprocessors Goals: • Reduced footprint with moderate short-channel effects • High performance at low voltage 5

Moore’s Law: it’s all about MOSFET scaling 1. New device structures with improved scalability: 2. New materials with improved transport characteristics: n-channel: Si  Strained Si  SiGe  InGaAs p-channel: Si  Strained Si  SiGe  Ge  InGaSb 6

Contents 7

1. Self-aligned Planar InGaAs MOSFETs dry-etched recess selective MOCVD W Mo Lin, IEDM 2012, 2013, 2014 Lee, EDL 2014; Huang, IEDM 2014 implanted Si + selective epi reacted NiInAs Sun, IEDM 2013, 2014 Chang, IEDM 2013 8

Self-aligned Planar InGaAs MOSFETs @ MIT W Mo Lin, IEDM 2012, 2013, 2014 1.0 V gs -V t = 0.5 V L g =20 nm R on =224  m 0.8 0.4 V I d (mA/  m) Recess-gate process: 0.6 • CMOS-compatible 0.4 0.2 • Refractory ohmic contacts 0.0 • Extensive use of RIE 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) 9

Highest performance InGaAs MOSFET • Channel: In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As • Gate oxide: HfO 2 (2.5 nm, EOT~ 0.5 nm) 3.45 mS/  m L g =70 nm: • Record g m,max = 3.45 mS/mm at V ds = 0.5 V • R on = 190 Ω.mm Lin, EDL 2016 10

Excess OFF-state current Transistor fails to turn off: L g =500 nm -5 10 V ds ↑ I d (A/  m) -7 10 -9 10 V ds =0.3~0.7 V step=50 mV -11 10 -0.6 -0.4 -0.2 0.0 V gs (V) OFF-state current enhanced with V ds  Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM 2013 11

Excess OFF-state current L g =500 nm -5 10 -4 10 T=200 K V ds ↑ V ds =0.7 V -5 I d (A/  m) 10 -7 10 I d (A/  m) -6 10 L g =80 nm -9 10 -7 10 120 nm V ds =0.3~0.7 V 280 nm step=50 mV -8 10 -11 10 500 nm -0.6 -0.4 -0.2 0.0 V gs (V) -0.6 -0.4 -0.2 0.0 V gs -V t (V) Simulations W/ BTBT+BJT w/ BTBT+BJT -5 10 W/O BTBT w/o BTBT+BJT Lin, EDL 2014 L g =500 nm I d (A/  m) Lin, TED 2015 -7 10 -9 10 L g ↓  OFF-state current ↑ V ds =0.3~0.7 V  bipolar gain effect due to floating body step=50 mV -11 10 -0.4 -0.2 0.0 0.2 V gs (V) 12

2. InGaAs FinFETs Intel Si Trigate MOSFETs 13

Bottom-up InGaAs FinFETs Aspect-Ratio Trapping Fiorenza, ECST 2010 Si Epi-grown fin inside trench Waldron, VLSI Tech 2014 14

Top-down InGaAs FinFETs dry-etched fins Radosavljevic, IEDM 2010 60 nm Kim, IEDM 2013 15

InGaAs FinFETs: g m g m normalized by width of gate periphery Natarajan, 2.0 Radosavljevic, 0.18 IEDM 2014 Si FinFETs IEDM 2011 5.3 0.23 1.8 4.3 0.57 1.5 channel 1 0.66 Kim, IEDM 2013 aspect g m [mS/  m] ratio 1.0 0.63 0.6 0.5 0.8 1 InGaAs FinFETs 0.0 0 20 40 60 Oxland, EDL 2016 Thathachary, W f [nm] VLSI 2015 • Narrowest InGaAs FinFET fin: W f =15 nm • Best channel aspect ratio of InGaAs FinFET: 1.8 • g m much lower than planar InGaAs MOSFETs 16

InGaAs FinFETs @ MIT Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Vardi, • Sub-10 nm fin width DRC 2014, • Aspect ratio > 20 EDL 2015, • Vertical sidewalls IEDM 2015 17

InGaAs FinFETs @ MIT Vardi, VLSI Tech 2016 • CMOS compatible process • Mo contact-first process • Fin etch mask left in place  double-gate MOSFET 18

InGaAs FinFETs @ MIT 1000 1600 L g =30 nm, W f =22 nm, H c =40 nm (AR=1.8): 800 1200 g m [  S  m  I d [  A  m] 600 1200 V GS = 0.75V 800 400 V DS =500mV 0.5 1000 400 200 H c I d [  A  m] W f =22 nm 800 0.25 L g =30 nm 600 0 0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 V GS [V] 400 0 200 1E-3 V DS =500 mV -0.25 0 -0.5 1E-4 50 mV 0.0 0.2 0.4 0.6 0.8 1.0 V DS [V] 1E-5 170 I d [A  m] Current normalized by 2xH c DIBL=220 mV/V 1E-6 S=140 mV/dec At V DS =0.5 V: W f =22 nm 1E-7 • g m =1.4 mS/µm L g =30 nm 1E-8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 • R on =170 Ω.µm V GS [V] • S sat =170 mV/dec Vardi, VLSI Tech 2016 19

Most aggressively scaled FinFET L g =20 nm, W f =7 nm, H c =40 nm (AR=5.7): 40 V GS = 0.75 V V DS =500 mV W f =7 nm 1E-5 L g =20 nm 0.5 50 mV 30 1E-6 S=120 mV/dec I d [  A  m] DIBL~150 I d [A  m] 1E-7 20 0.25 1E-8 10 0 -0.25 1E-9 0 1E-10 0.0 0.2 0.4 0.6 0.8 1.0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 V GS [V] V DS [V] At V DS =0.5 V: • g m =170 µS/µm • R on =4 kΩ.µm • S sat =130 mV/dec Vardi, VLSI Tech 2016 20

InGaAs FinFETs: g m benchmarking g m normalized by width of gate periphery: W f 2.0 0.18 Si FinFETs 5.3 0.23 H c 1.8 H c 4.3 0.57 1.5 1 0.66 1.8 g m [mS/  m] 2.3 1.0 0.63 0.6 3.3 0.5 0.8 5.7 1 InGaAs FinFETs Double gate Trigate 0.0 0 20 40 60 Vardi, VLSI Tech 2016 W f [nm] • First InGaAs FinFETs with W f <10 nm • Severe g m degradation for thin W f  sidewall roughness? 21

Latest results • Scaled gate oxide: HfO 2 with EOT=0.6 nm • Attention to line-edge roughness 2.0 Latest! 0.18 Si FinFETs 5.3 0.23 1.8 4.3 0.57 1.5 1 0.66 1.8 g m [mS/  m] 2.3 1.0 0.63 0.6 3.3 0.5 0.8 5.7 1 InGaAs FinFETs 0.0 0 20 40 60 Vardi, submitted 2016 W f [nm] Record results for InGaAs FinFETs with W f < 25 nm 22

InGaAs FinFETs: g m benchmarking g m normalized by fin width (FOM for density): 20 W f W f 5.3 Si FinFETs 15 4.3 H c H c g m /W f [mS/  m] EOT=1 nm (HfO 2 /Al 2 O 3 ) EOT=0.6 nm (HfO 2 ) 10 InGaAs FinFETs 1.8 5 1 0.66 3.32.31.8 0.18 0.23 1 0.57 0.63 0.6 0.8 5.7 0 0 20 40 60 Vardi, submitted 2016 W f [nm] • Doubled g m over earlier InGaAs FinFETs • Still far below Si FinFETs  poor sidewall charge control 23

Impact of fin width on V T InGaAs doped-channel FinFETs: 50 nm thick, N D ~10 18 cm -3 T=90K • Strong V T sensitivity for W f < 10 nm; much worse than Si • Due to quantum effects Vardi, IEDM 2015 24

3. Nanowire InGaAs MOSFETs Waldron, EDL 2014 Tanaka, APEX 2010 Persson, EDL 2012 Tomioka, Nature 2012 • Nanowire MOSFET: ultimate scalable transistor • Vertical NW: uncouples footprint scaling from L g and L c scaling 25

InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Selective-Area Epitaxy Vapor-Solid-Liquid (VLS) Technique Riel, MRS Bull 2014 Björk, JCG 2012 26

InGaAs VNW MOSFETs by top-down approach @ MIT Key enabling technologies: 15 nm • RIE = BCl 3 /SiCl 4 /Ar chemistry • Digital Etch (DE) = O 2 plasma oxidation H 2 SO 4 oxide removal 240 nm • Sub-20 nm NW diameter • Aspect ratio > 10 • Smooth sidewalls Zhao, EDL 2014 27

NW-MOSFET I-V characteristics: D=40 nm V gs =-0.2 V to 0.7 V in 0.1 V step 350 700 Bottom electrode as the source (BES) 300 V ds =0.5 V 600 250 I d  A/  m) 500 200 g m,pk (  S/  m ) 400 150 300 100 Zhao, 2016 200 50 (submitted) 100 0 0.0 0.1 0.2 0.3 0.4 0.5 0 V ds (V) -0.4 -0.2 0.0 0.2 0.4 V ds =0.5 V V gs (V) Single nanowire MOSFET: -4 10 • L ch = 80 nm -5 10 V ds =0.05 V • 3 nm Al 2 O 3 (EOT = 1.5 nm) I d ( A/  m ) -6 10 • g m,pk =620 μS/μm @ V DS =0.5 V S=98 mV/dec, V ds =0.05 V -7 10 S=110 mV/dec, V ds =0.5 V -8 • S sat =110 mV/dec @ V DS =0.5 V 10 DIBL = 177 mV/V -9 10 • Approaches best bottom-up devices [Berg, IEDM 2015] -0.4 -0.2 0.0 0.2 0.4 V gs (V) 28

Self-aligned Bottom-up InAs NW-MOSFETs Berg, IEDM 2015 VNW MOSFET array: • VLS growth • D=28 nm • L ch = 190 nm • g m,pk =850 μS/μm @ V DS =0.5 V • S sat =154 mV/dec @ V DS =0.5 V 29

How are we doing in terms of short-channel effects? Planar-MOSFET FinFET Ideal scaling S lin : linear subthreshold swing VNW MOSFET L g = gate length λ c = electrostatic scaling length: f(t ox , t ch ) • Reasonable scaling behavior but… • Excessive D it del Alamo, J-EDS 2016 30

4. InGaSb p–type MOSFETs Planar InGaSb MOSFET demonstrations: Nainani, IEDM 2010 Takei, Nano Lett. 2012 31

InGaSb p–type FinFETs @ MIT Key enabling technology: • BCl 3 /N 2 RIE • [digital etch under development] 20 nm fins, 20 nm spacing • Smallest W f = 15 nm • Aspect ratio >10 15 nm fins, AR>13 • Fin angle > 85 ° • Dense fin patterns Lu, IEDM 2015 32

InGaSb p-type FinFETs • Fin etch mask left in place  double-gate MOSFET • Channel: 10 nm In 0.27 Ga 0.73 Sb (compressively strained) • Gate oxide: 4 nm Al 2 O 3 (EOT=1.8 nm) Lu, IEDM 2015 33