Energy Efficient Com puting in Nanoscale CMOS Vivek De Intel - PowerPoint PPT Presentation

Energy Efficient Com puting in Nanoscale CMOS Vivek De Intel Fellow Director of Circuit Technology Research Intel Labs

I nternet of Everything ( I oE) 2 2

Moore’s Law scaling 3

Dynam ic platform control 4 4

Near Threshold Voltage ( NTV) com puting 5 5

NTV I A processor 6 6

NTV design techniques Narrow m uxes No stack height > 2 Robust level converters 7 7

NTV I A – pow ered by solar cell! 8 8

Pow er perform ance m easurem ents 9 9

Pow er com ponents Logic Dynamic Power Memory Dynamic Power Logic Leakage Power Memory Leakage Power 4% 1% 11% 3% 27% 33% 5% 15% 62% 81% 53% 5% Vcc-max (Super-Threshold) Vcc-opt (Near-Threshold) Vcc-min (Sub-Threshold) Logic Vcc: 1.2V Logic Vcc: 0.45V Logic Vcc: 0.28V Memory Vcc: 1.2V Memory Vcc: 0.55V Memory Vcc: 0.55V 1 0 10

Minim um energy operation 1 1 11

NTV and variability 1000 32nm CMOS, 25 o C 16% 30% Energy/Cycle (pJ) 28% 22% Fast Medium Slow Leakage Comparison 18% Slow 1.0X Medium 2.5X Fast 7.5X 100 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) 1 2 12

Voltage-frequency m argins 1 3 13

Dynam ic adaptation & reconfiguration 1 4 14

Dynam ic V & F adaptation 1 5 15

Resilient platform s 1 6 16

Resilient & adaptive core 1 7 17

Perform ance & efficiency gains 1 8 18

I ntegrated voltage regulators 1 9 19

Fully integrated VR 2 0 20

Energy efficient interconnects 2 1 21

Mem ory capacity & bandw idth 2 2 22

Efficient & scalable neurom orphic system s 2 3 23

Efficient & scalable neurom orphic architecture 2 4 24

The next big leap… 2 5 25

2 6 26