Ringamp: The Scalable Amplifier We ve All Been Waiting For? - PowerPoint PPT Presentation

THE “ IDEAL AMPLIFIER ” WISHLIST So ... how did we do? High linearity High bandwidth Ring Amplifier High gain Fast slewing (ringamp) Low noise Performance scales Rail-to-rail OUTm INp like digital CMOS output swing class-AB Small area Fully dynamic Low design effort (switchable) 41

TOPOLOGY SELECTION 42

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Dead-zone Signaling Signaling Number Number Power Power CMFB Other CMFB Other embedding mode of stages Cycling embedding mode of stages Cycling Biasing Biasing Pseudo- Pseudo- Fully- Fully- Auto- Auto- High- High- Location Device Location Device Mode differential differential zero voltage Mode differential differential zero voltage 43

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Dead-zone Signaling Number Power CMFB Other embedding mode of stages Cycling embedding Biasing Biasing Pseudo- Fully- Auto- High- Location Device Mode differential differential zero voltage Mode Class B Class AB Class B+AB 44

BIASING MODE TOPOLOGY SELECTION DC Input Sweep ▪ Class-B dead-zone ▪ Sub-threshold “ dead-zone ” ▪ Surrounded by “ weak-zone ” ☺ Fastest, most stable I OUT (mA)  Dead-zone distortion M CP C 2 RST RST V IN - V OUT V DZ1 + I OUT C 3 RST V TEST M CN weak-zones V IN (mV) 45

BIASING MODE TOPOLOGY SELECTION DC Input Sweep ▪ Class-AB weak-zone ▪ Only “ weak zone ” ▪ Always conducting ☺ Highest accuracy I OUT (mA)  Slower M CP C 2 RST RST V IN - V OUT V DZ1 + I OUT C 3 RST V TEST M CN V IN (mV) 46

BIASING MODE TOPOLOGY SELECTION ▪ Class-B + AB ▪ Class-B coarse charge ▪ Class-AB fine settle [Hershberg, VLSI 2013] 47

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Dead-zone Signaling Number Power CMFB Other embedding mode of stages Cycling embedding Biasing Pseudo- Fully- Auto- High- Location Device Location Mode differential differential zero voltage Directly before Earlier output stages stage 48

EMBEDDING LOCATION TOPOLOGY SELECTION ▪ Directly before output stage INp OUTm ▪ Precise control of output stage biasing ▪ Best for: ▪ Class-AB operation ▪ High accuracy & linearity [Hershberg, VLSI 2013] ▪ Low gain technologies ▪ Nanoscale CMOS 👎 INp OUTm [Lim, JSSC Oct. 2015] 49

EMBEDDING LOCATION TOPOLOGY SELECTION ▪ Before second-to-last stage ▪ Decouples stability from large signal biasing of output stage ▪ Best for: OUTm INp ▪ Class-B operation ▪ High speed ▪ Coarse charging [Hershberg, JSSC 2012] 50

TOPOLOGY CHOICES Basic Topology Selection Basic Topology Selection Dead-zone Dead-zone Signaling Number Power CMFB Other embedding mode of stages Cycling embedding Biasing Pseudo- Fully- Auto- High- Location Device Device Mode differential differential zero voltage CMOS Capacitor Resistor Resistor 51

CAPACITOR EMBEDDING TOPOLOGY SELECTION OUTm INp ▪ Direct voltage-mode control ▪ Best for ▪ Class-B biasing [Hershberg, JSSC 2012] ▪ High-voltage applications ▪ Limitations ▪ If embedding in last stage, will reduce INp OUTm max slewing efficiency [Hershberg, VLSI 2013] 52

RESISTOR EMBEDDING TOPOLOGY SELECTION ▪ Dynamically creates offset during stabilization INp OUTm ▪ Best for ▪ PVT robust design ▪ Nanoscale CMOS ▪ Slewing efficiency [Lim, JSSC Oct. 2015] ▪ Limitations ▪ Speed problems if large V DZ offset needs to be embedded 53

RESISTOR EMBEDDING TOPOLOGY SELECTION V OV + ▪ Dynamically creates offset during ─ stabilization + INp OUTm I D V DZ ▪ Best for - I OUT ▪ PVT robust design ▪ Nanoscale CMOS ▪ Slewing efficiency [Lim, JSSC Oct. 2015] ▪ Limitations If V DD I D V DZ I OUT ▪ Speed problems if large V DZ offset needs to increases increases increases stable be embedded If Temp decreases 54

RESISTOR EMBEDDING TOPOLOGY SELECTION ▪ Dynamically creates offset during stabilization + INp OUTm I D V DZ ▪ Best for - ▪ PVT robust design ▪ Nanoscale CMOS ▪ Slewing efficiency [Lim, JSSC Oct. 2015] ▪ Limitations ΔV DZ = I D * R B ω p = 1/RC ▪ Speed problems if large V DZ offset needs to be embedded Want a Needs Creates slow stage 2 poles  a big R big V? 55

CMOS RESISTOR EMBEDDING TOPOLOGY SELECTION ▪ Tunable on-state resistance ▪ Switchable (off-state) INp OUTm EN EN ▪ Best for ▪ Power-cycling ▪ Optimal biasing [Lagos, JSSC Feb. 2019] ▪ Nanoscale CMOS ▪ Limitations ▪ Less PVT robust than static resistor 56

OTHER EMBEDDINGS TOPOLOGY SELECTION ▪ Current starved inverters ▪ Best for Bn ▪ Dynamic control INp OUTm ▪ Analog PVT tracking schemes Bp ▪ Limitations Slower (lowers 2 nd stage output poles) ▪ [Hershberg, PhD Thesis 2012] [Leuenberger, CICC 2017] 57

OTHER EMBEDDINGS TOPOLOGY SELECTION ▪ Threshold voltage of output stage OUTm ▪ Best for ▪ Low supply voltages ▪ High speed ▪ Simplicity ▪ Area [Lim, JSSC Oct. 2015] ▪ Limitations ▪ PVT variation ▪ Not with high supply voltages 58

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Signaling Signaling Number Power CMFB Other embedding mode of stages Cycling mode Biasing Pseudo- Pseudo- Fully- Fully- Auto- High- Location Device Mode differential differential zero voltage differential differential 59

PSEUDO DIFFERENTIAL TOPOLOGY SELECTION ▪ Can be purely inverter-based, most dynamic INp OUTm ▪ Best for ▪ Speed ▪ Limitations CMFB ▪ Large input offset must be canceled ▪ Limited accuracy INm OUTp 60

FULLY DIFFERENTIAL TOPOLOGY SELECTION V DD ▪ Fully-differential ▪ Best for OUTm OUTm INm INp ▪ General purpose ▪ Highest accuracy V CMFB ▪ Limitations V SS ▪ Moderate speed /power penalty (front stage becomes slower) 61

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Signaling Number Number Power CMFB Other embedding mode of stages Cycling of stages Biasing Pseudo- Fully- Auto- High- Location Device Mode differential differential zero voltage 62

THREE-STAGE TOPOLOGY SELECTION VDD ▪ The “ workhorse ” EN EN EN EN Vs2p2 Vs2p1 ▪ Best for DZN DZN V DD V DD OUTp OUTm ▪ Most applications EN_i EN EN EN_i INp INm V DD V SS V SS DZP DZP EN Vs2m2 Vs2m1 ▪ Limitations EN EN_i EN_i ▪ Might not give enough gain in M CM2 M CM1 some technologies to support VSS calibration-free operation [Hershberg, ISSCC 2019] CMFB ▪ CMFB can be a little tricky in fully-differential topologies 63

FOUR-STAGE TOPOLOGY SELECTION ▪ When more gain is needed ▪ Best for ▪ High precision ▪ Calibration-free ▪ Limitations ▪ CMFB and latch-up require careful consideration ▪ A little less speed (extra internal pole) [Lim, VLSI 2017] 64

TWO-STAGE TOPOLOGY SELECTION ▪ Special purpose ▪ Best for ▪ Non-inverting feedback loop (e.g. CMFB) ▪ Low precision applications [Lagos, JSSC Feb. 2019] ▪ Limitations ▪ Low gain 65

ONE STAGE? TOPOLOGY SELECTION ▪ “ Inverter based amplifier ” ▪ Best for OUTm ▪ Specialty applications INp ▪ Limitations ▪ Low gain ▪ Low gain-bandwidth ▪ Low slew rate / slew efficiency ▪ No gain before output stage (no large-signal effects) ▪ A multi-stage ringamp is generally faster and more efficient. 66

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Signaling Number Power CMFB Other CMFB embedding mode of stages Cycling Biasing Pseudo- Fully- Auto- High- Location Device Mode differential differential zero voltage 67

TOPOLOGY SELECTION CMFB ▪ Approach varies depending on topology INp OUTm ▪ Psuedo-differential EN EN EN EN ▪ Fully-differential ▪ Level of CM rejection needed CMFB INm EN EN EN EN OUTp 68

TOPOLOGY SELECTION CMFB ▪ Approach varies depending on topology INp OUTm ▪ Psuedo-differential EN EN EN EN ▪ Fully-differential ▪ Level of CM rejection needed rst ▪ Passive CMFB VCM rst rst ▪ Simple rst ▪ Often good enough INm EN EN EN EN OUTp [Hershberg, JSSC 2012] 69

TOPOLOGY SELECTION CMFB ▪ Approach varies depending on topology INp OUTm ▪ Psuedo-differential EN EN EN EN ▪ Fully-differential ▪ Level of CM rejection needed 2-stage rst ringamp ▪ Passive CMFB A v VCM rst ▪ Simple rst ▪ Often good enough INm ▪ Active CMFB EN EN EN EN ▪ Add gain OUTp ▪ Higher accuracy ▪ Larger rejection range [Lagos, JSSC Feb. 2019] 70

TOPOLOGY SELECTION CMFB VDD ▪ Fully differential EN EN EN EN ▪ Often requires global and local loops Vs2p2 Vs2p1 DZN DZN V DD V DD ▪ 3 paths OUTp OUTm EN_i EN EN EN_i INp INm V DD V SS V SS ▪ DC bias DZP DZP EN Vs2m2 Vs2m1 ▪ Fast global feedback EN EN_i EN_i ▪ Fast local feedback M CM2 M CM1 VSS B1 Trapped Charge CMFB OUTp C FB C SENSE EN EN_i EN_i C SMALL EN_i C BIG C SENSE C FB OUTm [Hershberg, ISSCC 2019] 71

TOPOLOGY SELECTION CMFB VDD ▪ Fully differential EN EN EN EN ▪ Often requires global and local loops Vs2p2 Vs2p1 DZN DZN V DD V DD ▪ 3 paths OUTp OUTm EN_i EN EN EN_i INp INm V DD V SS V SS ▪ DC bias DZP DZP EN Vs2m2 Vs2m1 ▪ Fast global feedback EN EN_i EN_i ▪ Fast local feedback M CM2 M CM1 VSS B1 Trapped Charge CMFB OUTp C FB C SENSE EN EN_i EN_i C SMALL EN_i C BIG C SENSE C FB OUTm [Hershberg, ISSCC 2019] 72

TOPOLOGY SELECTION CMFB VDD ▪ Fully differential EN EN EN EN ▪ Often requires global and local loops Vs2p2 Vs2p1 DZN DZN V DD V DD ▪ 3 paths OUTp OUTm EN_i EN EN EN_i INp INm V DD V SS V SS ▪ DC bias DZP DZP EN Vs2m2 Vs2m1 ▪ Fast global feedback EN EN_i EN_i ▪ Fast local feedback M CM2 M CM1 VSS B1 Trapped Charge CMFB OUTp C FB C SENSE EN EN_i EN_i C SMALL EN_i C BIG C SENSE C FB OUTm [Hershberg, ISSCC 2019] 73

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Signaling Number Power Power CMFB Other embedding mode of stages Cycling Cycling Biasing Pseudo- Fully- Auto- High- Location Device Mode differential differential zero voltage 74

TOPOLOGY SELECTION POWER CYCLING ▪ Only operate when needed ▪ Save power INp OUTm ▪ Best solution very architecture dependent 75

TOPOLOGY SELECTION POWER CYCLING ▪ Only operate when needed ▪ Save power INp EN OUTm ▪ Best solution is very architecture dependent EN ▪ A naive solution: power gate + output switch Extra switch in feedback path  ▪ Undefined internal reset state  ▪ Signal dependent charge kickback  ▪ Clock must drive all switches on EN line  ▪ Headroom reduced by power gating switches  ▪ 76

TOPOLOGY SELECTION POWER CYCLING ▪ Only operate when needed ▪ Save power INp OUTm ▪ Best solution is very architecture dependent ▪ A better solution: full-reset, self-disconnect EN Extra parasitics from pullup/pulldown switches  ▪ Clock must drive all switches on EN line  ▪ Headroom reduced by power gating switches  ▪ 77

TOPOLOGY SELECTION POWER CYCLING ▪ Only operate when needed ▪ Save power INp OUTm ▪ Best solution is very architecture dependent ▪ A better solution: full-reset, self-disconnect EN Extra parasitics from pullup/pulldown switches  ▪ Clock must drive all switches on EN line  ▪ Headroom reduced by power gating switches  ▪ 78

TOPOLOGY SELECTION POWER CYCLING ▪ A very elegant solution: self-resetting INp OUTm ▪ Requires EN EN EN EN ▪ Bias-enhancement (we ’ ll get to this later) ▪ CMOS resistors ▪ Best of all worlds [Lagos, JSSC Mar. 2019] ▪ No power-gating switches ▪ No pull-up or pull-down switches ▪ Small switches (CMOS resistors) minimize clock loading 79

TOPOLOGY SELECTION POWER CYCLING ▪ A very elegant solution: self-resetting INp OUTm ▪ Requires EN EN EN EN ▪ Bias-enhancement (we ’ ll get to this later) ▪ CMOS resistors ▪ Best of all worlds [Lagos, JSSC Mar. 2019] ▪ No power-gating switches ▪ No pull-up or pull-down switches ▪ Small switches (CMOS resistors) minimize clock loading 80

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Signaling Number Power CMFB Other Other embedding mode of stages Cycling Biasing Pseudo- Fully- Auto- Auto- High- Location Device Mode differential differential zero voltage zero 81

TOPOLOGY SELECTION AUTO-ZERO ▪ Not for free ▪ Extra complexity ▪ Sometimes extra power ▪ Some applications / topologies require it ▪ Pseudo-differential ringamps ▪ Zero-offset applications ▪ Most applications / topologies can avoid it ▪ Offset tolerant and “ good enough ” use cases ▪ System level methods 82

TOPOLOGY SELECTION AUTO-ZERO ▪ Not for free INp OUTm ▪ Extra complexity ▪ Sometimes extra power CMFB ▪ Some applications / topologies require it ▪ Pseudo-differential ringamps ▪ Zero-offset applications INm OUTp ▪ Most applications / topologies can avoid it “ Good enough ” partial cancellation: ▪ Offset tolerant and “ good enough ” use cases 1. Inverter trip-point offset ▪ System level methods (tech. dependent V TH mismatch) 2. Stage 1 random offset (largest source of random offset) 83

TOPOLOGY SELECTION AUTO-ZERO C FB ▪ Not for free ▪ Extra complexity C S C AZ ▪ Sometimes extra power IN + OUT A v ▪ Some applications / topologies require it C L - ▪ Pseudo-differential ringamps ▪ Zero-offset applications β = 1 C LOAD = C L + C AZ ▪ Most applications / topologies can avoid it ▪ Offset tolerant and “ good enough ” use cases Be careful with C AZ sizing : ▪ System level methods Stability Noise [Lim, Oct. 2015] 84

TOPOLOGY SELECTION AUTO-ZERO C FB ▪ Not for free ▪ Extra complexity C S C AZ ▪ Sometimes extra power + OUT A v ▪ Some applications / topologies require it C L - VREF ▪ Pseudo-differential ringamps ▪ Zero-offset applications β = C S / C FB C LOAD = C L + C FB //C S ▪ Most applications / topologies can avoid it ▪ Offset tolerant and “ good enough ” use cases ▪ System level methods [Lim, Oct. 2015] 85

TOPOLOGY SELECTION AUTO-ZERO V DD ▪ Not for free ▪ Extra complexity OUTm OUTm INm INp ▪ Sometimes extra power V CMFB ▪ Some applications / topologies require it V SS ▪ Pseudo-differential ringamps ▪ Zero-offset applications Differential topologies: • No inverter trip-point offset ☺ ▪ Most applications / topologies can avoid it • Only random mismatch offset ▪ Offset tolerant and “ good enough ” use cases ▪ System level methods 86

TOPOLOGY SELECTION AUTO-ZERO Example: Pipelined SAR stage β ▪ Not for free V OS - + IN + + - + ▪ Extra complexity OUT - ringamp -V OS - ▪ Sometimes extra power + - + SAR CDAC Logic - ▪ Some applications / topologies require it ▪ Pseudo-differential ringamps Can often find simple methods to cancel ▪ Zero-offset applications ringamp offset somewhere else in the system ▪ Most applications / topologies can avoid it ▪ Offset tolerant and “ good enough ” use cases ▪ System level methods 87

TOPOLOGY SELECTION Basic Topology Selection Basic Topology Selection Dead-zone Signaling Number Power CMFB Other Other embedding mode of stages Cycling Biasing Pseudo- Fully- Auto- High- High- Location Device Mode differential differential zero voltage voltage 88

TOPOLOGY SELECTION HIGH-VOLTAGE ▪ Capacitor embedding is best ▪ Can store large ΔV needed to generate dead -zone ▪ Can level shift between different VDDs ▪ Can couple in multiple output paths (coarse/fine) [ElShater, JSSC 2019] 89

PATHWAYS TO PERFORMANCE 90

PATHWAYS TO PERFORMANCE My Ringamp Needs … My Ringamp Needs … More Settled Linearity More Settled Linearity More Speed More Speed Less Noise Less Noise Increase Increase Minimize Minimize Reduce Reduce Biasing Biasing Circuit Circuit Increase Increase Circuit Circuit Internal Internal Internal Internal output pole output pole Mode Mode Techniques Techniques Gain Gain Techniques Techniques Power Power Parasitics Parasitics frequency frequency 91

PATHWAYS TO PERFORMANCE My Ringamp Needs … My Ringamp Needs … More Settled Linearity More Settled Linearity More Speed Less Noise Increase Minimize Reduce Biasing Biasing Circuit Increase Circuit Internal Internal output pole Mode Mode Techniques Gain Techniques Power Parasitics frequency class-AB biasing (weak-zone only) 92

PATHWAYS TO PERFORMANCE My Ringamp Needs … My Ringamp Needs … More Settled Linearity More Settled Linearity More Speed Less Noise Increase Minimize Reduce Biasing Circuit Circuit Increase Circuit Internal Internal output pole Mode Techniques Techniques Gain Techniques Power Parasitics frequency External Gain Dead-zone Enhancement Degeneration Techniques 93

DEAD-ZONE DEGENERATION LINEARITY ENHANCEMENT [Lagos, JSSC Mar. 2019] DC Open-loop Gain (dB) ▪ Motivation 1 st order linear gain error often easy to calibrate ▪ (with digital or trimming) ▪ Higher order gain error much harder to correct ▪ Idea ▪ Feedback to “ warp ” V DZ as function of V OUT ▪ Especially useful in low-gain tech. like 28nm V DZ (mV) + INp OUTm V DZ VCM - V OUT (mV) 94

PATHWAYS TO PERFORMANCE My Ringamp Needs … My Ringamp Needs … More Settled Linearity More Settled Linearity More Speed Less Noise Increase Minimize Reduce Biasing Circuit Circuit Increase Circuit Internal Internal output pole Mode Techniques Techniques Gain Techniques Power Parasitics frequency External Gain Dead-zone Enhancement Degeneration Techniques 95

EXTERNAL GAIN ENHANCEMENT TECHNIQUES LINEARITY ENHANCEMENT ▪ Class-AB style ringamps compatible with many “ classical ” gain enhancement techniques ▪ Ringamps using Correlated Level Shifting (CLS) techniques: ▪ Split-CLS [Hershberg, JSSC 2012] ▪ A-CLS [T.C. Hung, JSSC 2019] ▪ WA-CLS [T.C. Hung, JSSC 2020] [T.C. Hung, JSSC 2020] 96

PATHWAYS TO PERFORMANCE My Ringamp Needs … My Ringamp Needs … More Settled Linearity More Settled Linearity More Speed Less Noise Increase Minimize Reduce Biasing Circuit Increase Increase Circuit Internal Internal output pole Mode Techniques Gain Gain Techniques Power Parasitics frequency Cascade Boost More per-Stage Stages Gain 97

PATHWAYS TO PERFORMANCE My Ringamp Needs … My Ringamp Needs … More Settled Linearity More Speed More Speed Less Noise Increase Minimize Minimize Reduce Biasing Circuit Increase Circuit Internal Internal Internal output pole Mode Techniques Gain Techniques Power Parasitics Parasitics frequency 98

THE 2 COMMANDMENTS OF HIGH SPEED RINGAMP DESIGN 1. Thou shalt never load the internal nodes 2. Thou shalt never limit the internal currents 99

THE 2 COMMANDMENTS OF HIGH SPEED RINGAMP DESIGN ▪ But many choose to break the rules... ▪ Trade speed for other benefits Current limiter for peak g m /I D OUTm INp [Lim, JSSC Oct. 2015] 100