Atomic level material processing and characterization for nanoscale - - PowerPoint PPT Presentation

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Atomic level material processing and characterization for nanoscale CMOS transistors

Toshihiko Kanayama Nanodevice Innovation Research Center, AIST, Japan MIRAI project

JST - DFG Joint Workshop January 21, 2009

2/24

New Materials and Structures for Ultra-scaled MOSFET

Keeping Ioff low and enhancing Ion by optimal selection of materials and structures

Si

Planar FET

SiGe, SiC, MSix, MGex

→

Si Source/Drain Metal, Metal Silicide

→

Poly-Si Gate Electrode High-k Dielectrics (HfSiO, HfAlO, LaAlO)

→

SiO2 (SiON) Gate Dielectrics High-mobility Materials （Strained Si, SiGe, Ge)

→

Si Channel Future Present

Materials evolution for high drive current Structure evolution for gate control

SiO2、High-k

Source Drain

Gate SiGe Strained Si、SiGe

Multi-gate FET Strained SOI、SGOI FET

埋め込み酸化膜 Source Drain

メタル ゲート

BOX BOX

Gate

3/24

Increasing Requirements for Metrology and Characterization Technology

Porous Low-k reliability issue Cu Voiding due to Stress/ Electro migration Strained Si, SiGe Metal S/D High-k Dopant diffusion and fluctuation Size variation Side wall roughness Metal Gate

Major Issues

• Technology boosters, i.e., new materials/structures and

processes are rushing into semiconductor technology.

• Variability increases.

To implement new technologies while minimizing variation, reliable characterization and metrology technologies are crucially needed.

CD & LER Potential/Dopant distribution Strain distribution Pore size, connectivity Mechanical strength

4/24

Contents For the fabrication of Nano CMOS Transistors What do we need?

• Gate stack (Gate dielectrics and electrode)
• Channel
• Source/Drain

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Si NiSi HfO2 HfSiOx 0.4nm 1nm

LOP( hp45,32,22) LSTP( hp45,32,22)

HfAlON

10

• 8

10

• 6

10

• 4

10

• 2

10

2

0.5 1.0 1.5 2.0 2.5 3.0 Gate Leakage Current 【A/cm2】 equivalent oxide thickness【nm】

SiO2

LOP( hp45,32,22) LSTP( hp45,32,22) HfAlON

10

• 8

10

• 6

10

• 4

10

• 2

1 10

2

0.5 1.0 1.5 2.0 2.5 3.0

：MIRAI ：MIRAI

Other

• rganizations

HfSiON

This technique

NiSi Si HfSiOx HfO2 1 Cycle Si Anneal HfO2 Si CC-D&A*

Gate Electrode Interfacial layer

750℃ Deposition

Cycle-by-Cycle Deposition & Annealing

• A. Ogawa et al., INFOS (2007)

Towards EOT (equivalent oxide thickness) =0.5nm

Source Drain Gate

Ion

Ileak

Si

6/24

Control of threshold voltage

SiO2

Top high-k

Gate

Bottom high-k

Si

Gate Fermi Level Pinning

0.5 1.0 1.5 2.0

0.2 0.4

VFB (V)

HfO2 Al2O3

Thickness of bottom high-k film (nm)

Top : HfO2 Bottom : Al2O3 Top : Al2O3 Bottom : HfO2

Si HfO2 Al2O3 NiSi

Energy Ｏｆｆｓｅｔ

Dipole formation

Iwamoto, VLSI Symp. 2007

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Contents For the fabrication of Nano CMOS Transistors What do we need?

• Gate stack (Gate dielectrics and electrode)
• Channel: Surface flatness

S G D Multi-Gate (Nanowire) Transistor

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Atomically flattening of Si surfaces

Si(001) Si(110) 200nm□ Si(111)

Low pH HF treatment + Hydrogen anneal（800℃）

AFM measurement of Sidewall roughness Before H2 anneal （after RIE） H2 annealed：800℃, 0.1 torr, 40 s

(SPM + RCA+ LPH + H2 anneal)

Line profile

9/24

Atomic Precision CD Metrology by AFM

CD-AFM with Laser interferometer Resolution 0.05 nm

Modularized Laser interferometer 0.25 nm 0.1 nm 0.05 nm

0.5 1.0 1.5 2.0 4 5 6 7 8 9

Time (sec) Displacement (nm)

Size of hydrogen atom

• S. Gonda et al., Characterization and

Metrology for ULSI Tech., 2005 3D AFM scanner: parallel spring mechanism. Laser interferometer: DSP-based processing.

Sidewall and line edge roughness measured by tilt-step-in operation

• K. Murayama et al, SPIE, 2006

ArF resist/ Low-k patterns

H=200nm Y (nm) 20 40 60 80 100 10 20

X (nm)

H=400nm Y (nm) 20 40 60 80 100 10 20

X (nm) X Y Z

240 nm

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(a) HF-treatment (oxide removal, H-termination) (b) RTA 700˚C (N2 1torr: H-desorption) (c) H2O exposure 250˚C (Formation of Si-OH)

H

Si sub.

O H H

(a) H-terminated surface (b) H-desorption 700˚C N2 (c) Hydrophilicized surface H2O exposure 250˚C

H H H H

Si sub.

H H

Si sub.

O H O H H

Surface hydrophilicization

0.2 0.4 0.6 0.8 1 1.2 2 4 6 8 10

Hydrophilicized EOT (nm)

1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 2 4 6 8 10

Inserted Al2O3 cycles

Jg@VFB-1V (A/cm2) HF-last Hydrophilicized

Inserted Al2O3 cycles

Si

Al2O3

HfO2 NiSi

Morita, SSDM 2008

11/24

Ge-pMOSFET with Lg=60nm

Si passivation for Gate stack, NiGe Metal S/D

50nm NiGe NiGe TaN

n-Ge

50nm NiGe NiGe TaN

n-Ge

7ML Si Epi-layer

Quasi-ballistic transport

Velocity

100 1000 10000 5 10 50 100 500 Gate length LG (nm) GM SAT Max. (mS/mm)

COX VSAT Ge VD = -1.0V

VSAT Ge = 6E6cm/s : 4.4E15cm -3 : 1.3E17cm -3 : 3.3E17cm -3 : 7.0E17cm -3 Channel conc. slope 1/ LG

Yamamoto et al. IEDM, 2007

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Uni-axially Strained Multi-Gate CMOS Transistors

pMOSFET

Uni-axial Compressive strain on SiGe (110) surface

• T. Irisawa et al., IEDM, 2005

SSOI Gate (001) <110>

SSOI Poly BOX 45 nm 50 nm SSOI Poly BOX 45 nm 50 nm

nMOSFET

Uni-axial tensile strain on Si (110) surface

0.05 0.1 0.15 0.2 0.25 0.3 0.35

• 0.5

0.5 1 1.5 2

gm (μS) Vg (V) SSOI Tri-gate SOI Tri-gate

2.2x Lg = 10 μm Vd = 0.05 V Wfin = 50 nm Id // <110>

• T. Irisawa et al. IEDM, 2006

SGOI Gate <110>

pMOS SiGe SiN Poly-Si 55 nm NiSi SiO2 90 nm 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08

• 2
• 1.5
• 1
• 0.5

0.5 Vg-Vth (V) Gm x Tox / W (mS) Lg= 0.4 μm Vd= -50 mV

×3

SGOI Fin (110) Uniaxially strained SOI Planar (100) Unstrained

(110) (100) (110)

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NBD (NanoBeam electron Diffraction)

SiGe(x,z)=(5.469Å,5.504Å) Si(x,z) =(5.474Å,5.417Å) Si(x,z)=(5.433Å,5.433Å)

Z X Si sub. 100nm Box 35nm SiGe 17nm St-Si 70nm Tensile strain SiGe St-Si Si

Strained-Si Relaxed- SiGe buffer layer Poly-Si

Strain in a MOSFET channel

Usuda, Materials Sci. Eng. B124–125 (2005) 143

Lg=1 μm X-axis Z-axis e--beam

14/24

λ= 675 nm for AFM To spectrometer Position- sensitive detector AFM probe λ= 364 nm

Confocal/probe-excited UV Raman microscope for local strain analysis

x μｍ y μｍ strong weak Compressive stress

2D Raman mapping

SiO2 Si

Raman Shift (1/cm) ×103

Poborchii, Appl. Phys. Lett. 89 (2006) 233505

1 μm

Excitation λ=364 nm, φ～130 nm Raman scattering Si SiO2

Raman shift： １／λout－ １／λin = phonon vibration For strain ε in Si Δ( １／λ)＝723 ε cm-1

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Raman Measurements on (110) Cross Section of STI Structure

SiO2 Si [110] a [001] b [1-10] c

（１１０） Cross Section

Δωs

［001］Uniaxial

Doublet 520.5 cm-1 Singlet Δωd

［110］Uniaxial

I1

520.5 cm-1

I2 I3

Δω2

Δω3

Δω1

☆(a/b) ☆(a/a) ☆(a/b) ☆(a/a) （c/b）

Resolving Axial Components

Δωab=C1σ（100）＋C2σ（110） Δωab=C3σ（100）＋C4σ（110） Trench Bottom

50000 50500 51000 51500 200 400 600 800

Position (nm) Stress (MPa)

σ

xx

[110]

σ

zz[001]

515 520 525 530 500 1000 1500 2000

520.85

ab

Intensity, a.u. Raman Shift, cm

• 1

aa

521.23

Polarization (Excitation/Detection)

Tada, SSDM 2008

16/24

Contents

For the fabrication of Nano CMOS Transistors

What do we need?

• Gate stack (Gate dielectrics and electrode)
• Channel: Surface flatness,

high-mobility material, Local strain

• Source/Drain: Dopant profiling for ultra-shallow junction, metal

source/drain

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Simultaneous measurement of potential and individual dopant atoms Donor distribution correlates with the potential fluctuation.

40 nm

Vs = +1.7 V, It = 6 pA 40 nm

acceptors (blue spot) donors (red spot) n p

n: As 10 keV,

5x1013 cm-2

p: B 10 keV

1.5x1013 cm-2

Imaging of dopant atoms

Substrate bias voltage: Vs acceptor

negative charge

donor

positive charge

Vs Vs>0 Vs<0

Key process Flattening and hydrogenation of (111) surface by NH4F treatment followed by dopant reactivation at ～400°C

Nishizawa, Appl. Phys. Lett. 90 (2007) 122118. Tunneling Current Cross Section

• f MOSFET

STM Probe Gate Source Drain

Kanayama, A-3-1

I-V

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Local Work Function Measurements on a Transistor Cross Section

X:

30 nm below surface

170 nm D S Channel

100 200 300 400 500

1 2 3

Position (nm) (dI/dZ) (arb.u.)

Y: Gate Edge

90 nm

D D G G

100 200 300 400 500

1 2 3

Position (nm) (dI/dZ ) (arb.u.)

90 nm

D D G G

100 200 300 400 500

1 2 3

Position (nm) (dI/dZ ) (arb.u.)

Y X

0.5×0.5μm２ (b) Local Work Function

S/D： 35keV As 2×1015cm-2

dZ

A

dI

VZ dVZ Zo Vo STM probe Si

SiO2

Vacuum-Gap Modulation

⇨ local work function ∝

ultra-thin oxide

dI/dz Lg=35 nm

Bolotov, SSDM 2008

19/24

Quantitative potential profiling by I-V measurements

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Position Sample Bias Voltage (V)

40 nm Vs = +1.7 V, It = 6 pA

~0.9 V

Depletion~50 nm Tunnel Current (nA)

n p

• M. Nishizawa et al, APL 2007
• 2
• 1

1 2

• 100
• 50

50 CBM = EFtip VBM = EFtip ～0.9 eV Distance (nm)

n: 2×1019cm-3

abrupt junction

p: 1×1018cm-3

Sample Bias Voltage (V) surface junction vacuum n: 1×1017cm-3 p: 1×1017cm-3 X (μm) Z (μm)

Potential simulation

probe Band Bending VBB Vacuum gap VBM Efs CBM e- Eft Vgap Vs Si Issues

• Potential distortion by

STM bias

• Vs=Vgap+VBB

unknown

Sample Bias Voltage (V)

I-V measurement

STS

(scanning tunneling spectroscopy) CBM VBM

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Metal S/D Formation using Epitaxial NiSi2

Nickel film Si

Si(100), 500oC 1min

NiSi NiSi2

1 10 100

Silicide (nm)

1 10 100

Ni (nm)

Self-limiting

t0.5

1

2 4 6

10

2 4 6

100

NiSi2 (nm)

1 10 100

Time (min)

NiSi2 lattice diffusion

N-doped Ni Sputtered with Ar/N2 gas

Self-limiting behavior in NiSi2 growth

Migita, SSDM 2008

21/24

NiSi NiSi2

500 nm

100 nm 100 nm

LG LCh

10 nm

700 nm

SEM TEM

Silicidation: N-doped Ni and 500oC anneal

Application to Nanowire Transistor

Metal S/D Formation using Epitaxial NiSi2

Straight edge is automatically formed.

22/24

towards “Ballistic” Transistors

Metal gate S Source Box Source Drain

Lg～15 nm

Channel Metal S/D

STM probe

Local workfunction/barrier height measurements by STM Metal S/D, High-k/Metal Gate sub-10 nm FET Barrier height control by dopant segregation at the NiSi2/Si interface

e Reduction of interface scattering Box Si e Si + +

• +

+

• +

+

• +

+

• High-k insulator (MSiOx)

Metal Metal S/D Atomically flat interface Barrier height control

23/24

Conclusions Conclusions

For Nano CMOS Fabrication;

• Atomic scale processing technologies are requires

particularly at the interface of heterogeneous materials. – Full exploitation of Self-limiting or self-organizing phenomena

• Nanoscale characterizations of local properties and

structures are needed. – e.g., Local strain in Si, Potential distributions

24/24

Acknowledgments Acknowledgments

Colleagues in MIRAI project

• T. Tada and V.V. Porochii for UV Raman measurements
• L. Bolotov and M. Nishizawa for STM measurements
• K. Usuda for Nano-beam diffraction
• N. Hirashita, T. Numata, T. Tezuka, N. Sugiyama and S. Takagi and many
• ther members of the MIRAI project for providing STI and strained SOI

structures Sample preparation

• N. Hattori of Renesas Technology for strained STI structures
• H. Fukutome of Fujitsu Laboratory Ltd. for the p-n junction samples.

This work was supported by MIRAI project, NEDO and by METI under the Innovation Research Project on Nanoelectronics Materials and Structures.