A Novel DPS Integrator for Fast CMOS Imagers J. M. Margarit, J. - PowerPoint PPT Presentation

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 1/17 A Novel DPS Integrator for Fast CMOS Imagers J. M. Margarit, J. Sabadell, L. Terés and F. Serra-Graells System Integration Department Institut de Microelectrònica de Barcelona Centro Nacional de Microelectrónica - CSIC Spain May 2008 J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 2/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 3/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 4/17 FPA In-pixel ADC ◮ Architecture? Digital Pulse�density�modulator filter X Direct (flash) I sens X Algorithmic (success. approx.) + q adc V pulse � Predictive ( Σ∆ ) - DAC ◮ Feedback = relaxed analog specs ◮ Pulse modulator + digital filter I sens V int q adc + PWM ≡ time-to-first spike 0 V pulse - V th PDM ≡ spike counting � No external clocks 0 � Switching power ∝ signal b init X Signal loss due to reset times J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 5/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 6/17 PDM for Fast Imaging b init + V pulse ◮ Classic topology: C int ◮ CTIA to cancel I sens C CDS V int input parasitics b init + V pulse V pulse ◮ Correlated double C par sampling ( CDS ) for noise cancellation V ref V V + ref th ◮ Ideally : T pulseideal = T frame T frame q adc = ⌊ n adcideal ⌋ n adcideal = C int V th I sens J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 7/17 Real Scenario T frame ◮ Loss due to b init reset time : V + V ref th T frame V int n adcreal = V ref T pulseideal + T res 1 2 3 4 5 6 7 V pulse n adcideal n adcreal = T pulseideal T res 1 + T frame n adcideal T pulsereal ◮ Non-linearity error: V V + ref th V int V ref n error = | n adcreal − n adcideal | 1 2 3 4 5 6 V pulse ◮ Maximum at full-scale : T res q fullscale Not compatible Tframe q fullscale < 0 . 5 LSB = 1 max ( n error ) = q fullscale − Tres 2 1+ with low-power T frame T res < for q fullscale ≫ 1 nor low-voltage ! 2 q 2 fullscale e.g. q fullscale = 1023(10 bit ) T frame = 10 ms ⇒ T res < 5ns J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 8/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 9/17 Reset-Insensitive Topology b init ◮ Charge controlled reset of the PDM integrator C int I sens ◮ Continuous-time V int integration (like APS!) V pulse V pulse C par ◮ Built-in CDS mechanism C reset/CDS V ref V V + ref th ◮ Switch charge injection similar to classic topology J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 10/17 Real Scenario T frame ◮ During reset, charge b init from I sens and C reset / CDS is combined V V + ref th V int and integrated in C int . V ref 1 2 3 4 5 6 7 V pulse ◮ Almost ideal , even for T pulseideal T pulsereal ∼ T res . T pulsereal V V + ref th V int V ref ◮ Minimum T res required 1 2 3 4 5 6 7 V pulse for redistribution. . . T res True low-power ◮ . . . but T res value not and low-voltage relevant ( technology compatible! independence ). J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 11/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 12/17 CMOS Proposal I bias I bias I bias ◮ 3-stage compact V int b init PDM circuit I sens V pulse V pulse V pulse C int C reset/CDS V ref ◮ Single transistor CTIA stage M1 C par M1 M2 M3 ◮ Local reference M2 ◮ Technology mismatching ◮ Built-in threshold C int ↔ C reset / CDS , M1 ↔ M2 and M1 ↔ M3 comparator M3 (all in are equivalent to ∆ V th weak inversion): V th = nU t ln ( W / L ) 1 ◮ ∆ V th reduction through DPS area increase ( W / L ) 3 J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 13/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 14/17 Quasi-Static (QS) Stimulus Classic�PDM Proposed�PDM 1 1000 0.5 1 0.2 0.1 0.5 800 0.2 Digital�output�[LSB] 600 0.1 400 200 0 0 1 2 3 4 5 0 1 2 3 4 5 ◮ 0.18 µ m 1-poly 6-metal ◮ Design parameters : CMOS technology C int , reset / CDS =100fF, V ref =1V, ( W / L ) 1 =20 ( W / L ) 3 so V th =0.1V and T frame =2ms J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 15/17 Non Quasi-Static (NQS) Stimulus Classic�PDM Proposed�PDM 1000 800 Digital�output�[LSB] 600 400 200 0 0 1 2 3 4 5 0 1 2 3 4 5 ◮ Non systematic loss even at low amplitudes for classic PDM 0 T frame time J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 16/17 1 Introduction 2 Reset Issues in Spike Counting 3 Novel PDM Scheme 4 Compact CMOS Realization 5 Simulation Results 6 Conclusions J. M. Margarit et al. Centro Nacional de Microelectrónica

ISCAS’08: A Novel DPS for Fast CMOS Imagers Intro Reset-Issues Novel-PDM CMOS Results Conclusions 17/17 Conclusions ◮ Novel pulse density modulator (PDM) for high-speed DPS. ◮ Reset-insensitive analog integrator proposal. ◮ Low non-linearity for low-power and low-voltage operation. ◮ Compact CMOS circuit realization. ◮ Comparative study in 0.18 µ m 1-poly 6-metal technology. ◮ Robust simulation results for both QS and NQS signals. J. M. Margarit et al. Centro Nacional de Microelectrónica