A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS - PowerPoint PPT Presentation

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 1/19 A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers F. Serra-Graells, J. M. Margarit and L. Terés System Integration Department Institut de Microelectrònica de Barcelona Centro Nacional de Microelectrónica - CSIC Spain May 2007 F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 2/19 1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 3/19 1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 4/19 Scenario Active pixel requirements sensor�FPA CMOS�read-out ◮ Hybrid imager ⇒ array high input cap ◮ Room temp. IR ⇒ large dark current digital digital gain image map map ◮ FPA signal integrity ⇒ digital only I/O ◮ FPN compensation ⇒ individual pixel gain programmability hybrid pad ◮ Large FPA ⇒ (bumping, ADC I/O postprocess...) low-power & compact pixel circuits digital�pixel�sensor�(DPS) F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 5/19 1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 6/19 ◮ Automatic input dark Digital pixel sensor (DPS) proposal current & capacitance compensation V com ◮ Asynchronous ADC digital�programming-in bin based on spike counting ◮ Individual gain control: DPS cell offset cancel. local�bias � FPN compensation digital integrator I dark ADC C int � Spatial AGC I sens I eff V int + V spike I/O V th � Updated each frame analog DAC integrator C par comp. individual�gain�control � No speed reduction C par digital�read-out bout ◮ Built-in analog references F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 7/19 1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 8/19 Input offset and capacitance compensation ◮ Low impedance input: C dark M6 � � 1 1 M8 r in = ≪ 1 k Ω gm g 1 , 2 gm g 5 n + M7 gm d 1 , 2 + gm d 3 , 4 I bias I dark so, C par can be >10pF. . . I eff cal I bias M1 M2 ◮ Regulated cascode M5 dark current copier : M3 M4 � Mismatch insensitive C par � Large dark-to-signal ratio ∼ 1 µ A I sens 1 nA V com F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 9/19 ◮ 3-switch reset Integrating ADC CTIA stage: � More parasitic I bias M17 insensible M18 I eff M9 V spike � Constant input M12 M13 voltage V spike C int V int M10 M11 I bias � CDS implementation V spike I bias M14 M16 M15 M19 � Low-power V th Class-AB ◮ Fast reset times can be obtained. Ideally: ◮ Dynamic bias comparator 1 f spike = I eff C int V th ◮ C int linearity not needed F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 10/19 Digital integrator and I/O ◮ Circuit reuse : V spike count � Ripple counter count init init � Shift register 1... N init init bin qin qout qin qout bout count ein eout ein eout clk clk ◮ Modular design clk clk init ◮ Overflow detector count qin qout ◮ In case of no overflow: D Q Q Q clk D Q wout = f spike = T frame I eff ein eout init M20 f frame C int V th F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 11/19 Self-biasing ◮ Local I / V reference: M24 M23 M26 � Low crosstalk I bias � Compact circuit M21 M22 P 1 V ref ◮ Low process sensitivity M25 ◮ Bias mismatching between DPS cells: (M21-M22 in weak inv. + M25 in strong inv.) � ∆ V ref � 1 A VTO σ = V ref � nV ref ( WL ) 21 , 22 V ref = U t ln ( P ) � W � I bias ≃ β ( V DD − V TO ) V ref L 25 F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 12/19 FPN compensation ◮ Offset cancellation already gain�code�sequence addressed by the input copier bin ◮ Built-in DAC for gain correction: b i V int V spike edac V th N b N − i � V th = V DD count clk clk 2 i i = 1 C mem C samp edac � No speed reduction shift register DPS mode � Individual for each DPS bout � Changeable each frame image�code�sequence ◮ Suitable for spatial AGC F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 13/19 1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 14/19 CMOS integration (first version) ◮ Room temperature PbSe IR sensor target gnda gnda pad ◮ Design parameters : C int 500 fF vdda vdda N 10 bit P 12 gndd gndd I bias 50 nA C mem , samp 100 fF vddd vddd gndd gndd ◮ 0.35 µ m 2-polySi 4-metal vddd vddd CMOS technology gndd gndd 10 m ¹ 100 µ m × 100 µ m F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 15/19 CMOS integration (first version) ◮ Room temperature PTAT PbSe IR sensor target C int M6 ◮ Design parameters : ( C dark ) Analog�integrator cal cal and�ADC C int 500 fF N 10 bit edac edac P 12 DAC C mem C samp I bias 50 nA C mem , samp 100 fF clk Digital�integrator clk ninit ninit and�I/O ◮ 0.35 µ m 2-polySi 4-metal count count qin qout CMOS technology 10 m ¹ 100 µ m × 100 µ m F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 16/19 Results (first version) ◮ Test vehicle: � 3 × 10 pixel FPA � NMOS sensor emulator ◮ Performance: Dark current range 0.1-5 µ A Dark current retention time 2-10 s Max. input capacitance 15 pF Signal range 1-1000 nA Integration time 1 ms Crosstalk <0.5 LSB Programming/read-out speed 10 Mbps Supply voltage 3.3 V Static power consumption <1 µ W Biasing deviations ( ± σ ) ± 15 % 100 × 100 µ m 2 Total Silicon area F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 17/19 Last minute results (second version) ◮ Shared DAC for programming V th & I dark at alternating frames: digital I dark control for V th = ’1000000000’ digital V th control for I dark = ’1000000000’ '1000000000' '1000000000' '1111111111' '0100000000' Digital�read-out�[LSB] Digital�read-out�[LSB] '0110000000' '1100000000' '1010000000' '0100000000' '1100000000' '0000000000' I sens [nA] I sens [nA] F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 18/19 1 Introduction 2 Pixel Architecture Proposal 3 Low-Power CMOS Building Blocks 4 Experimental Results 5 Conclusions F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona

ISCAS’07: A Digital APS for Hybrid CMOS Imagers Intro DPS Blocks Results Conclusions 19/19 Conclusions ◮ Novel low-power and digital-only I/O DPS cell ◮ Hybrid imager compatibility ◮ Pixel built-in FPN compensation and biasing generation ◮ Circuit implementation for all building blocks ◮ 0.35 µ m 2-polySi 4-metal CMOS demonstrator F. Serra-Graells, J. M. Margarit and L. Terés Institut de Microelectrònica de Barcelona