IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 1/19 A Self-Biased PLL-Tuned AER Pixel for High-Speed Infrared Imagers J.M. Margarit, M. Dei , L. Terés and F. Serra-Graells josepmaria.margarit@imb-cnm.csic.es Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC) May 2011 J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 2/19 1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 3/19 1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 4/19 DPS Introduction Focal plane array MWIR ◮ Uncooled MWIR PbSe Digital pixel sensor (DPS) VPD technology V com Arbitrer ◮ High-speed (>1Kfps) PbSe sensor I sens vision for automotive, CMOS process control. . . read-out circuit Encoder Event address ◮ Compact and low-power CMOS circuits V com req ack ◮ High dark-to-signal Temporal Analog Window contrast current ratios integrator comparator AER interface I sens I int V int ◮ Tunable temporal pos neg contrast to match I bias applications Non-stop reset I tune reset ◮ High-speed spiking PLL High-speed spike generation f tune insensitive to AER delay Digital tuning tune outp outn J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 5/19 1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 6/19 Log-Domain Temporal Contrast V com 1 N ◮ Dark current cancellation M6 M7 ◮ Emphasis on high-freq. contents I sens I bias ◮ Self-biasing capability I int C int V int I tune I bias ◮ I -domain low-pass linear ODE V tune I sens M4 dI bias = 2 π f c ( I sens − I bias ) V bias M5 dt M2 M1 M3 I cap V sens C bias ◮ Subthreshold companding (M1-M2) N 1 N VGB − VTO − VSB I D = 2 n β U 2 e nUt e Ut t � �� � I S ◮ V -domain non-linear ODE (M3-M4) � � C bias dV bias Vsens − Vbias = 2 π f c nU t C bias e nUt − 1 dt � �� � � �� � I tune I cap J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 7/19 Log-Domain Temporal Contrast ◮ Dark current cancellation ◮ Corner frequency tuning ◮ Emphasis on high-freq. contents 0 100f ◮ Self-biasing capability 10f -20 1f -40 -60 ◮ I -domain low-pass linear ODE Gain [dB] -80 dI bias = 2 π f c ( I sens − I bias ) -100 dt I tune =1nA -120 100p 10p ◮ Subthreshold companding (M1-M2) -140 1p -160 VGB − VTO − VSB I D = 2 n β U 2 e nUt e Ut -180 t 1m 10m 100m 1 10 10 1K 10K 100K 1M 10M � �� � Frequency [Hz] I S ◭ I tune programmability ? ◮ V -domain non-linear ODE (M3-M4) � � C bias dV bias Vsens − Vbias = 2 π f c nU t C bias e nUt − 1 dt � �� � � �� � I tune I cap J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 8/19 1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 9/19 Reset-Insensitive High-Speed AER reset (a) ◮ CTIA -based integration for C int high-speed imaging ( C int ↓ ) I int V int ◭ Spiking frequency non-linearity at high-rate due to AER delay : V ref | I int | f req f ′ req = f req = 1 + t res f req C int V th J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 10/19 Reset-Insensitive High-Speed AER reset (a) (b) ◮ CTIA -based integration for C int C int high-speed imaging ( C int ↓ ) I int I int V int V int ◭ Spiking frequency non-linearity at high-rate due to AER delay : reset V ref | I int | f req V ref + V th V ref C res f ′ req = f req = 1 + t res f req C int V th C int C int (c) (d) reset reset I int ◮ Novel reset-insensitive schemes V int C res based on charge injection : I int reset V int • Inherent CDS ? V ref C res • Extra capacitors? V ref • Low-impedance sources? Dead Voltage Cap time CDS sources area (a) � � × × (b) � × ×× × (c) � � × × (d) � � � × J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 11/19 Reset-Insensitive High-Speed AER I bias M4 ack pos I bias ack ◮ CTIA -based integration for pos I int V int M2 M5 C int high-speed imaging ( C int ↓ ) 1/ P pos init pos neg ◭ Spiking frequency non-linearity at neg I bias ackd high-rate due to AER delay : M1 MC int 1 M7 neg | I int | f req ackd f ′ M6 req = f req = neg 1 + t res f req C int V th init ackd M3 P pos ◮ Novel reset-insensitive schemes neg ack ackd based on charge injection with req inherent CDS t res ack pos ack ◮ Compact and low-power CMOS M8 pos outp circuit realization pos req V th = ± nU t M ln ( P ) t arb ack t ack ack neg outn outp Time J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 12/19 1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 13/19 PLL-Based Tuning Charge PFD pump VCO tune1 slow ◮ Temporal contrast f c X 1 1 M7 tune2 V ctrl M3 M2 M1 ◭ Weak integrity pA-range I tune M8 I tune fast M6 tune1 vco ◮ Digital frequency tuning based V vco M4 M5 tune1 1 Y C vco on in-pixel PLL : I tune tune1 f tune = 2 V thvco C vco tune2 � � 1 + Y V vco V thvco V thvco = nU t ln 1 + 1 / X vco slow ◮ Robust KHz-range clocking fast ◮ Process and thermal Time compensation for I tune � � f c = 1 C vco 1 + Y ◮ Dynamic and adaptive contrast? C bias ln f tune π 1 + 1 / X J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 14/19 1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 15/19 CMOS Design Example outp outn gnd gnd ◮ 0.35 µ m 2P4M CMOS technology ◮ Design parameters: I dark ≃ 1 µ A, N =4, C int =80fF, M =3/2, P =4, X =1, Y =2 and C vco / C bias =15 req req PbSe pad ◮ 40 µ m- pitch DPS ack ack tune1 tune1 tune2 tune2 init init vdd vdd outp outn 10 m ¹ J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 16/19 CMOS Design Example ◮ 0.35 µ m 2P4M CMOS technology 10M ◮ Design parameters: I dark ≃ 1 µ A, N =4, C int =80fF, M =3/2, P =4, 1M f req [Hz] X =1, Y =2 and C vco / C bias =15 100K ◮ 40 µ m- pitch DPS ◮ Good 0.12MHz/nA linearity up to the spiking rate hard limit 10K 100p 1n 10n 100n t arb + t ack ≃ 27MHz 1 I int [A] J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 17/19 CMOS Design Example 10M ◮ 0.35 µ m 2P4M CMOS technology 1M ◮ Design parameters: I dark ≃ 1 µ A, 100K N =4, C int =80fF, M =3/2, P =4, f c [Hz] X =1, Y =2 and C vco / C bias =15 10K 1K ◮ 40 µ m- pitch DPS 100 ◮ Good 0.12MHz/nA linearity up to the spiking rate hard limit 10 10 100 1K 10K 100K 1M 10M t arb + t ack ≃ 27MHz 1 f tune [Hz] typical mean, 27ºC ◮ Process and temperature typical mean, 60ºC compensation for the temporal worse speed, 27ºC contrast f c ◮ Power consumption ∝ 2 I dark J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 18/19 1 DPS Introduction 2 Log-Domain Temporal Contrast 3 Reset-Insensitive High-Speed AER 4 PLL-Based Tuning 5 CMOS Design Example 6 Conclusions J.M. Margarit et al. IMB-CNM(CSIC)
IEEE ISCAS 2011 DPS Contrast AER Tuning Example Conclusions 19/19 Conclusions ◮ Novel DPS circuit for uncooled MWIR PbSe sensors ◮ Log-domain filtering for temporal contrast and self-biasing ◮ AER insensitive spike generation with inherent CDS ◮ Digital PLL-based temporal contrast tuning with process and thermal compensation ◮ A 40 µ m-pitch DPS design example in 0.35 µ m 2P4M CMOS technology ◮ Currently, a 128 × 128 imager is under development in 0.15 µ m 1P6M CMOS technology. . . Thanks for your attention! J.M. Margarit et al. IMB-CNM(CSIC)
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