Low power, small die-size PLL using semi-digital storage instead of - PowerPoint PPT Presentation

Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance Presented by: Markus Dietl 1

Outline • Conventional PLL design approach / Proposed PLL design architecture • Circuit description of major blocks • Mathematical modeling of the PLL loop in Z-domain • Simulation results / LAB measurements • Scope for further development (future work) 2

Problem statement/ Introduction • To design a low bandwidth PLL (Bandwidth ~1-2KHz) • Very low power(< 500uA) • Low rms Jitter,C2C Jitter & period Jitter • Low die-size (aggressive pricing) • No External component 3

Traditional PLL concepts (Propotional Damping/Storage) Traditional: R t " ! V ( n ) Icp i = " R prop T update V ( n ) V ( n ) V ( n ) Icp = + + control prop stored n Icp t C # " V ( n ) i ! = stored C i 0 = f ( n ) K V ( n ) = ! 0 control 4

Proposed PLL (at n th update) Analog Damping used R t " ! V ( n ) Icp n = " with ripple cap R prop T Icp update + n Icp t C # " i V ( n ) ! = stored C i 0 = Replaced by Semi-digital storage (M storage cells) M f ( n ) K V ( n ) K ( n ) = " V ! + ! prop step j prop j 0 = 5

PLL during locking 2R Analog Damping Icp 1 R t " ! i V ( n ) Icp 2R = " prop 1 T update C storagecell_1 Icp2_1 OSC_ring V 1 ( n ) 0 Held digitally low < > = For Analog tuning Two active cells C storagecell_x Icp2_x n Icp t # " V x ( n ) 2 i ! < > = C Storagecell X & X+1 activ _ i 0 = C storagecell_x+1 activ n Icp t Icp2_x+1 # " V x 1 ( n ) 2 i ! < + > = C _ i 0 = activ C storagecell_M Icp2_n V M ( n ) VDD < > = Held digitally high M f ( n ) K ( VDD V ( n )) K ( n ) = # V 6 ! " + ! prop step j prop j 0 =

Proposed PLL block Diagram Ripple cap VCO tuning with 2 analog & N-2 digital bits PVT compensation With digital/semi-digital information REFCUR N Storage cells 7

Voltage controlled Oscillator Propotional Analog damping Wide VCO Range 8

Storage Cells & control PVT compensated Charge pump 9 N Semi-digital storage cells

APLL/DPLL/Proposed Semi-digital PLL Characteristic Analog PLL Digital PLL Proposed PLL Bandwidth(with 10K-1/10 th of <1Hz-1MHz <1Hz -1/10 th of onchip compon- Reference freq. Reference freq. ents only) Quantization NO Yes NO noise Simplicity Yes NO Yes Noise CP/LPF/Resistane Quantization due to low VCO noise gets noise gain, CP/ amplified with high Resistance noise VCO gain amplification is negligible 10

VCO gain from semi-digital storage (spice simulation): VCO acts linear (no freq. step) 20 VCO steps, from 30 to 50 VCO behaves like having N*vdd tuning voltage with very low gain 11

Z-Modeling of the PLL PLL_1 ___ ______________________________________ _____________________ _____________________ _______________________ dt[s] prop relative outpu tperio d change feed back devider VCO gain [Hz/step] 6 77 10 6 10 6 ! I p 15 10 N 2344 f t K p 78 6 6 ! := " := := # := " dt 70 10 K o 0.4 10 := # := " ___ ______________________________________ _____________________ _____________________ _______________________ s f t Tper -> Tphase in: 16 10 3 9 ! K o R C 1.2 10 f up := # := # := f up FB := N VC O Z s ( ) e 1 := f t 2 f2p s ( ) := 1 vdd C 1 ! ! 1 dt $ ' storagecel l 2 Z s ( ) = K p # % ( f t 2 Icp FB % ( 2 1 1 VC O AB s ( ) f2p s ( ) I p f up := # # # # + # % ( 1 Z s ( ) dt Z s ( ) 1 ! s C % ( + # R & ) N AB s ( ) 1 H Z s ( ) G Z s ( ) N AB s ( ) E Z s ( ) := := := 1 N AB s ( ) 1 N AB s ( ) + + _____________________________________________________________________________________ 10 x x 1 1.02 8 f x ( ) s f x ( ) 2 * f x ( ) i := , .. := , := # # # MAGNITUDE 4 2 0 ( ) 20 log E Z s f x ( ( ) ) # , 2 ! ( ) 20 log H Z s f x ( ( ) ) # , 4 ! 6 ! 8 ! 10 ! 1 10 3 1 10 4 1 10 5 10 100 " " " f x ( ) 12

Z-Modeling of PLL– Weak & Strong PLL_1ws 1.2 10 9 ! C := " ___ ___________________________________________ ___________________________________________ _____ ____________ dt[s] prop relative outpu tperio d change VCO gain [Hz/step] 10 6 ! I pw 14.6 10 6 10 6 18 10 3 := # 84 10 6 K ow 0.4 K pw 58 Rw ! := # := # := " dtw := " 10 6 ! I ps 15.8 64 10 6 10 6 10 6 14 10 3 := # ! dts K os 0.52 K ps 98 Rs := " := # := # := " _____________________________________________________________________________________ 10 x x 1 1.02 8 f x ( ) s f x ( ) 2 ! f x ( ) i := , .. := , := " " " MAGNITUDE 4 2 0 ( ) 20 log E Zs s f x ( ( ) ) " , ( ) 20 log H Zs s f x ( ( ) ) " , 2 $ ( ) 20 log E Zw s f x ( ( ) ) " , 4 $ ( ) 20 log H Zw s f x ( ( ) ) " , 6 $ 8 $ 10 $ 1 10 3 1 10 4 1 10 5 10 100 # # # 13 f x ( )

PLL CLOSED LOOP spice simulation nom 14

Closed loop Bandwidth Simulations (spice ) -1.25dB @ 1KHz 0dB @ 200Hz -6.5dB @ 3KHz -3dB @ 2KHz 15

Phase noise plot (lab measurement) 16

Lab Measurement: C2C & period Jitter 17

Conclusion • Proposed is a new PLL architecture for low bandwidth applications • No External capacitor is needed here. • Power consumption of the device is very low • Ripple capacitor is reduced by 1/15 th and performance is equivalent to the device with PLL having an external capacitance and bigger die size. • Scope for further work 18

Scope for further work • We will explore this architecture for High bandwidth PLL ’ s • We have plan to check this architecture for bandwidth <1Hz; for Jitter cleaner applications • There is a scope for further chip size reduction by sharing the capacitor used in storage cells for active & inactive cells 19

Thanks for joining the presentation Markus Dietl / Puneet Sareen TI-Germany Phone: ++49/8161/80 3237 ++49/8161/80 3540 E-Mail: m-dietl1@ti.com p-sareen@ti.com 20

Backup slides 21

Z domain Model of a conventional PLL PLL is a Loop that will create a Period, and compare the resulting edge at t_sys with the edge of the Reference Clock at t_ref. Control Voltage t_ref T ref + T sys PFD CP/ -K LF Delta_t f 2 1/z(s) t_sys T sys * N Z(s):= exp(-s Tref) + N 1/z(s) 22

Capacitance: Current to Voltage PFD produces each update a pulse with the width ! t i . During this time the charge pump current is flowing. So a charge will be deposited, with the size of: Q ( i ) Icp t = " ! i After n updates the total deposited charge is: n Q ( n ) Icp t ! = # " i i 0 = The capacitance translates that into : ! t i U stored n Icp t IP2 + 1/C # " U ( n ) i ! = 1/z(s) stored C i 0 = 23

Resistance: Current to Voltage PFD produces each update a pulse with the width ! t i . During this time the charge pump current is flowing and produces a voltage drop over the damping resistor, with the size of: V ( i ) R Icp = ! The rest of the update period no voltage drop is produced, so the average voltage drop is: t " U ( i ) i R Icp = ! ! prop T update ! t i U stored R/T update Icp 24

Z domain Model of a voltage / word controlled PLL V/DCO Control Voltages CHARGE R/Tref K_prop IP Delta_t f 2 PFD T ref - t_ ref 1/z(s) + T sys + K_step + f 2 . dt 1/z(s) 1/z(s) Stored Period T sys * N Z(s):= exp(-s Tref) + N t_sys vdd C ! 1/z(s) dt storagecel l 2 = Icp 2 Forward ( Z ) H ( Z ) = 1 Forward ( Z ) Feedback ( Z ) + K _ prop K _ step R 1 1 N ( I ) " " + " p 2 T 1 2 z ( s ) 1 ref 1 1 f f dt ! ! " H ( Z ) z ( s ) z = K _ prop K _ step N R 1 1 1 ( I ) + " " + " p 2 T 1 2 z ( s ) 1 ref 1 1 f f dt ! ! " z ( s ) z 25