Future of Nano CMOS Technology IEEE EDS WIMNACT 32 February 10, - PowerPoint PPT Presentation

Future of Nano CMOS Technology IEEE EDS WIMNACT 32 February 10, 2012 Hiroshi Iwai, Tokyo Institute of Technology 1

First Computer Eniac: made of huge number of vacuum tubes 1946 Big size, huge power, short life time filament  dreamed of replacing vacuum tube with solid-state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption 2

Mechanism of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) G Surface Gate electrode Gate Oxd Channel Drain Source S D Electron flow Positive bias for gate 0 bias for gate Surface Potential (Negative direction) Negative 0V 0V N + -Si P-Si N + -Si P-Si 1V 1V N-Si N-Si Source Channel Drain Source Channel Drain

1960 : First MOSFET by D. Kahng and M. Atalla Top View Al SiO 2 Si Si/SiO 2 Interface is exceptionally good 4

1970,71: 1st generation of LSIs 4bit MPU Intel 4004 1kbit DRAM Intel 1103 5

2011 Most recent SD Card 6

Most Recent SD Card 128GB (Bite) = 128G X 8bit = 1024Gbit = 1.024T(Tera)bit 1T = 10 12 = １ Trillion World Population ： 6 Billion Brain Cell ： 10 ～ 100 Billion Stars in Galaxy ： 100 Billion 7

Most Recent SD Card 8

2.4cm X 3.2cm X 0.21cm Volume ： 1. 6cm³ Weight ： 2g Voltage ： 2.7 - 3.6V Old Vacuum Tube ： 5cm X 5cm X 10cm, 100g,100W 1Tbit = 10k X10k X 10k bit Volume = 0.5km X 0.5km X 1km = 0.25 km 3 = 0.25X10 12 cm 3 Weight = 0.1 kgX10 12 = 0.1X10 9 ton = 100 M ton Power = 0.1kWX10 12 =50 TW Supply Capability of Tokyo Electric Power Company: 55 BW 9

So, progress of IC technology is most important for the power saving!

Downsizing of the components has been the driving force for circuit evolution 1900 1950 1960 1970 2000 Vacuum Transistor IC LSI ULSI Tube 10 µ m 10 cm cm mm 100 nm 10 -7 m 10 -5 m 10 -3 m 10 -2 m 10 -1 m In 100 years, the size reduced by one million times. There have been many devices from stone age. We have never experienced such a tremendous reduction of devices in human history. 11

5 nm gate length CMOS Is a Real Nano Device!! 5 nm Length of 18 Si atoms H. Wakabayashi et.al, NEC IEDM, 2003 12

Question: How far we can go with downscaling?

Surface Gate electrode Gate Oxd Channel Drain Source 0 bias for gate Surface Potential (Negative direction) Tunneling @Vg=0V, Negative 0V Transistor cannot N + -Si P-Si be switched off 1V 3nm N-Si Source Channel Drain 14

Prediction now! Limitation for MOSFET operation Tunneling distance Lg = Sub-3 nm? 3 nm Below this, no one knows future! 15

How far can we go for production? Now In 40 years: 18 generations, Past 0.7 times per 3 years Size 1/300, Area 1/100,000 1970 年 10 µ m  8 µ m  6 µ m  4 µ m  3 µ m  2 µ m  1.2 µ m  0.8 µ m  0.5 µ m  0.35 µ m  0.25 µ m  180nm  130nm  90nm  65nm  45nm  32nm Future  (28nm)  22nm  16nm  11.5 nm  8nm  5.5nm?  4nm?  2.9 nm? ・ At least 4,5 generations to 8nm ・ Hopefully 8 generations to 3nm

Subtheshold leakage current of MOSFET Id Ion OFF ON Subthreshould Leakage Current Ioff Vg Vg=0V Subthreshold Vth region (Threshold Voltage) 17

Log scale Id plot Vth cannot be decreased anymore Log Id per unit gate width (= 1 µ m) Ion 10 -3 A 10 -4 A significant Ioff increase 10 -5 A Ioff Vdd 10 -6 A down-scaling Vth: 300mV  100mV 10 -7 A Ioff increases Vdd=0.5V Vdd=1.5V 10 -8 A with 3.3 decades Vth (300 – 100)mV/(60mv/dec) 10 -9 A Ioff = 3.3 dec down-scaling 10 -10 A Vth = 300mV Vg (V) Subthreshold slope (SS) Vth = (Ln10)(kT/q)(C ox +C D +C it )/C ox = 100mV > ~ 60 mV/decade at RT Vg = 0V SS value: Constant and does not become small with down-scaling 18 18

Subtheshold leakage current of MOSFET Id Subthreshold Current Is OK at Single Tr. level Ion OFF ON But not OK For Billions of Trs . Subthreshould Leakage Current Ioff Vg Vg=0V Subthreshold Vth region (Threshold Voltage) 19

The limit is deferent depending on application 100 e) 10 Operation Frequency (a.u.) 1 Subthreshold Leakage (A/ µ m) 20 Source: 2007 ITRS Winter Public Conf.

Scaling Method: by R. Dennard in 1974 Wdep : Space Charge Region 1 (or Depletion Region) Width 1 1 Wdep has to be suppressed 1 S D Otherwise, large leakage I Wdep between S and D Leakage current Potential in space charge region is 0 high, and thus, electrons in source are 0 1 V attracted to the space charge region. K=0.7 X , Y , Z : K, V : K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V /N a K I Wdep : K I : K 0 0 K V 21 21

Down scaling is the most effective way of Power saving. The down scaling of MOSFETs is still possible for another 10 years! 3 important technological items for DS. New materials 1. Thinning of high-k beyond 0.5 nm 2. Metal S/D New structures 3. Wire channel