CENG 342 – Digital Systems Finite State Machine with Datapath (FSMD) Larry Pyeatt SDSM&T
Finite State Machine with Datapath (FSMD) A Finite State Machine with Datapath (FSMD) is a mathematical abstraction that is sometimes used to design complex digital logic devices or computer programs. An FSMD is a digital system composed of a finite-state machine, which controls the order of operations, and a datapath, which performs data processing operations. FSMDs are algorithms in which statements have been scheduled into states. A program is converted into a state diagram in which states and arcs may include arithmetic expressions, and those expressions may use external inputs and outputs as well as variables. A simple FSM does not use variables or arithmetic operations/conditions, thus FSMDs are more powerful than FSMs. The FSMD level of abstraction is often referred to as the register-transfer level (RTL). The FSMD abstraction is equivalent to the Turing machine in power, which means that any computable function can be implemented by the appropriate FSMD.
FSMD In the FSM (controller), each state assigns values to a set of datapath control signals which completely specifies the behavior of the datapath. However, when there are too many control signals it is difficult to realize what and how the datapath will operate. To improve on the FSM model, we use variable assignment statements to indicate changes in variable values stored in the datapath. An FSMD (FSM with datapath) can be viewed as a FSM model with assignment statements added to each state.
Formal Definition of FSMD Formally, a finite-state machine with datapath is a 6-tuple defined as follows: P = < S , s 0 , I ∪ STAT , O ∪ A , f , h > where S = { s 0 , . . . , s m } is a finite set of states s 0 is the reset state. I = { i j } is a set of primary input values. O = { o k } is a set of primary output values. A = { x ⇐ e : x ∈ VAR , e ∈ EXP } is a set of storage assignments. VAR is a set of storage variables. EXP = { f ( x , y , z , ... ) : x , y , z , ... ∈ VAR } is a set of expressions. STAT = { Rel ( a , b ) : a , b ∈ EXP } is a set of status signals as logical relations between two expressions from the set EXP . f is a state transition function that maps a cross product of S and I ∪ STAT into S . For Moore models, h is the output function that maps S into O ∪ A . For Mealy models, h is the output function that maps a cross product of S and I ∪ STAT into O ∪ A
Informal Definition of FSMD Basically it is a finite state machine, which has states, inputs and ouputs, controlling a datapath, which has data inputs, storage elements (variables), and operations that can be performed on the data. Consider the algorithm for counting the number of ’1’ bits in a data word. Data ← Input ⊲ Load the input data into Data Count ← 0 ⊲ Initialize counter while Data � = 0 do ⊲ Examine each bit in Data if LSB ( Data ) = 1 then ⊲ If the current least significant bit is 1 Count ← Count + 1 ⊲ Increment count end if Data ← LSR ( Data , 1 ) ⊲ Logical shift Data right by 1 bit end while How many variables are there?
Informal Definition of FSMD Basically it is a finite state machine, which has states, inputs and ouputs, controlling a datapath, which has data inputs, storage elements (variables), and operations that can be performed on the data. Consider the algorithm for counting the number of ’1’ bits in a data word. Data ← Input ⊲ Load the input data into Data Count ← 0 ⊲ Initialize counter while Data � = 0 do ⊲ Examine each bit in Data if LSB ( Data ) = 1 then ⊲ If the current least significant bit is 1 Count ← Count + 1 ⊲ Increment count end if Data ← LSR ( Data , 1 ) ⊲ Logical shift Data right by 1 bit end while How many variables are there? Two Variables: Data and Count (the input is not a variable).
Informal Definition of FSMD Basically it is a finite state machine, which has states, inputs and ouputs, controlling a datapath, which has data inputs, storage elements (variables), and operations that can be performed on the data. Consider the algorithm for counting the number of ’1’ bits in a data word. Data ← Input ⊲ Load the input data into Data Count ← 0 ⊲ Initialize counter while Data � = 0 do ⊲ Examine each bit in Data if LSB ( Data ) = 1 then ⊲ If the current least significant bit is 1 Count ← Count + 1 ⊲ Increment count end if Data ← LSR ( Data , 1 ) ⊲ Logical shift Data right by 1 bit end while How many variables are there? Two Variables: Data and Count (the input is not a variable). Each variable requires a register in the datapath.
Informal Definition of FSMD Basically it is a finite state machine, which has states, inputs and ouputs, controlling a datapath, which has data inputs, storage elements (variables), and operations that can be performed on the data. Consider the algorithm for counting the number of ’1’ bits in a data word. Data ← Input ⊲ Load the input data into Data Count ← 0 ⊲ Initialize counter while Data � = 0 do ⊲ Examine each bit in Data if LSB ( Data ) = 1 then ⊲ If the current least significant bit is 1 Count ← Count + 1 ⊲ Increment count end if Data ← LSR ( Data , 1 ) ⊲ Logical shift Data right by 1 bit end while How many variables are there? Two Variables: Data and Count (the input is not a variable). Each variable requires a register in the datapath. What operations must be performed?
Informal Definition of FSMD Basically it is a finite state machine, which has states, inputs and ouputs, controlling a datapath, which has data inputs, storage elements (variables), and operations that can be performed on the data. Consider the algorithm for counting the number of ’1’ bits in a data word. Data ← Input ⊲ Load the input data into Data Count ← 0 ⊲ Initialize counter while Data � = 0 do ⊲ Examine each bit in Data if LSB ( Data ) = 1 then ⊲ If the current least significant bit is 1 Count ← Count + 1 ⊲ Increment count end if Data ← LSR ( Data , 1 ) ⊲ Logical shift Data right by 1 bit end while How many variables are there? Two Variables: Data and Count (the input is not a variable). Each variable requires a register in the datapath. What operations must be performed? Four operations: Data ← Input , Count ← 0, Count ← Count + 1, and Data ← LSR ( Data , 1 ) .
One’s Counter – The Datapath We usually co-design the datapath and controller, refining each incrementally. But let’s just jump to the end in this case. We will load a number into a shifter. If the least significant bit (LSB) is one, then increment the counter. Shift right, and repeat. Shift E Right Shifter with Parallel Load Load_Shifter Load LSB Data !=0 Count E Counter Reset_Counter Reset Output Eanable
Specifying the FSM Our initial design is a literal translation of the algorithm. We can use a “next-state and output table with variable assignments.” Next State Control Datapath Current Start, Data Outputs Outputs State 00 01 10 11 Done Output Datapath Actions s 0 s 0 s 0 s 1 s 1 0 Z s 1 s 2 s 2 s 2 s 2 0 Z Data ← Input s 2 s 3 s 3 s 3 s 3 0 Z Count ← 0 0 Z Mask ← 1 s 3 s 4 s 4 s 4 s 4 s 4 s 5 s 5 s 5 s 5 0 Z Temp ← Data ∧ Mask s 5 s 6 s 6 s 6 s 6 0 Z Count ← Count + Temp s 6 s 4 s 7 s 4 s 7 0 Z Data ← Data ≫ 1 s 7 s 0 s 0 s 0 s 0 1 Count
Specifying the FSM – Part 2 From the above observations, we obtain a reduced table called a state-action table for specifying FSMDs. Current Next State Control and Datapath Actions State Condition, State Condition, Actions � � � � Start = 0 s 0 Output ← Z s 0 Start = 1 s 1 Done ← 0 s 1 s 2 Data ← Input s 2 s 3 Count ← 0 s 3 s 4 Mask ← 1 s 4 s 5 Temp ← Data ∧ Mask s 5 s 6 Count ← Count + Temp � � Data > 0 s 4 s 6 Data ← Data ≫ 1 Data = 0 s 7 � � Done ← 1 s 7 s 0 Output ← Count
Specifying the FSM – Part 3 From the above observations, we find that we can combine some states, and simplify some calculations. This is a Moore design, because none of the outputs are conditional (They only depend on the current state). Current Next State Control and Datapath Actions State Condition, State Condition, Actions � � � � Start = 0 s 0 Output ← Z s 0 Start = 1 s 1 Done ← 0 � � Data ← Input s 1 s 5 Count ← 0 s 5 s 6 Count ← Count + Data [ 0 ] � � Data > 0 s 5 s 6 Data ← Data ≫ 1 Data = 0 s 7 � � Done ← 1 s 7 s 0 Output ← Count
Example: One’s Counter In a Moore version of the FSMD: all the variable assignments (register loads) must be executed unconditionally in a state and only next states are to be selected conditionally. has five states output logic is simple since it is dependent only on the present state. In a Mealy version of the FSMD: the variable assignments (register loads) can be executed conditionally together with the conditional selection of next states. has four states output logic is more complex since it includes external and internal conditions.
One’s Counter – Final State-Action Table Current Next State Control and Datapath Actions State Condition, State Condition, Actions Output ← Z � � Start = 0 s 0 Done ← 0 s 0 Start = 1 s 1 Data ← Input Count ← 0 Data LSB = 1 s 2 s 1 Data � = 0 ∧ Data LSB = 0 s 3 Data = 0 s 4 s 2 s 3 Count ← Count + 1 Data LSB = 1 s 2 s 3 Data � = 0 ∧ Data LSB = 0 Data ← Data ≫ 1 s 3 Data = 0 s 4 � � Done ← 1 s 4 s 0 Output ← Count
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