CENG 342 Digital Systems Barrel Shifter Larry Pyeatt SDSM&T - PowerPoint PPT Presentation

CENG 342 – Digital Systems Barrel Shifter Larry Pyeatt SDSM&T

Barrel Shifter: Definition A barrel shifter is a digital circuit that can shift a data word by a specified number of bits without the use of any sequential logic. In other words, it is a combinational logic circuit. A barrel shifter is implemented with a chain of i 2-to-1 multiplexers, each shifting an n -bit word by either zero or 2 k bit positions, where 0 ≤ k < i , i is the number of bits in the shift amount, and typically, n = 2 i . Barrell shifters can be designed to perform any shift or rotate operation. Early computers used shifters that could only shift one bit at a time, or used sequential logic to perform multi-bit shifts. Barrell shifter design was a hot research topic in 2002. MS thesis at Lehigh University Research Paper from Princeton

Barrel Shifter: Example This is ann 8-bit barrell shifter that performs Logical Shift Right. 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0

Barrel Shifter VHDL has built-in shift functions ( sll , srl , rol , ror ), but they cannot be synthesized sometimes, so we need to design these circuits manually. Barrel Shifter: a digital circuit that can shift/rotate a specified amount of bits to the right. Assume an 8-bit data input and a 3-bit control signal to specify the amount to be shifted/rotated. Example: input is "11110000" and control signal is "011", the output is: 10000111 Input signal: a: in std_logic_vector(7 downto 0); Output signal: y: out std_logic_vector(7 downto 0) Shift amount: amt: in std_logic_vector(2 downto 0); Entity declaration: 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity barrel_shifter is 5 port( a: in std_logic_vector(7 downto 0); 6 amt: in std_logic_vector(2 downto 0); 7 y: out std_logic_vector(7 downto 0) 8 9 ); 10 end barrel_shifter;

Using selected signal assignment 1 architecture sel_arch of barrel_shifter is 2 begin with amt select 3 y<= a when "000", 4 a(0) & a(7 downto 1) when "001", 5 a(1 downto 0) & a(7 downto 2) when "010", 6 a(2 downto 0) & a(7 downto 3) when "011", 7 a(3 downto 0) & a(7 downto 4) when "100", 8 a(4 downto 0) & a(7 downto 5) when "101", 9 a(5 downto 0) & a(7 downto 6) when "110", 10 a(6 downto 0) & a(7) when others; -- 111 11 12 end sel_arch; This design is straightforward and easily understood, but for more than 8 bits, the code will become cumbersome, and it will make synthesis difficult. An alternate is to construct the circuit by stages. Assume 3-bit amt is m 2 , m 1 , m 0 . The total rotated amount is 4 m 2 + 2 m 1 + m 0 . To achieve this, in the n th stage is controlled by the n th bit of amt and shifts/rotates by n n or zero, depending on the control bit.

Using staged design 1 architecture multi_stage_arch of barrel_shifter is signal s0, s1: std_logic_vector(7 downto 0); 2 3 begin -- stage 0, shift 0 or 1 bit 4 s0 <= a(0) & a(7 downto 1) when amt(0)=’1’ else a; 5 -- stage 1, shift 0 or 2 bits 6 s1 <= s0(1 downto 0) & s0(7 downto 2) when amt(1)=’1’ else s0; 7 -- stage 2, shift 0 or 4 bits 8 y <= s1(3 downto 0) & s1(7 downto 4) when amt(2)=’1’ else s1; 9 10 end multi_stage_arch ;

Testing To test the circuit, we can simply write a user constraint file ( .ucf ) as below to map the signals to the S3 board pins. 8-bit switch for the input signal; 3 push button switches for the amt signal and the 8 discrete LEDs (not 7-segment LED) for output. 10 # 8 discrete LEDs (output) 11 NET "y<0>" LOC = "K12"; 1 # 8 slide switches (input) 12 NET "y<1>" LOC = "P14"; 2 NET "a<0>" LOC = "F12"; 13 NET "y<2>" LOC = "L12"; 3 NET "a<1>" LOC = "G12"; 14 NET "y<3>" LOC = "N14"; 4 NET "a<2>" LOC = "H14"; 15 NET "y<4>" LOC = "P13"; 5 NET "a<3>" LOC = "H13"; 16 NET "y<5>" LOC = "N12"; 6 NET "a<4>" LOC = "J14"; 17 NET "y<6>" LOC = "P12"; 7 NET "a<5>" LOC = "J13"; 18 NET "y<7>" LOC = "P11"; 8 NET "a<6>" LOC = "K14"; # 3 push buttons (input as control signal) 19 9 NET "a<7>" LOC = "K13"; 20 NET "amt<0>" LOC = "M13"; 21 NET "amt<1>" LOC = "M14"; 22 NET "amt<2>" LOC = "L13";

Testing – alternative Instead of writing a new .ucf file, we can also design a simple testing circuit and use the default s3 .ucf , which defines connections for ports named sw , btn , and led , among other things. 1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity shifter_test is port( 6 sw: in std_logic_vector(7 downto 0); 7 btn: in std_logic_vector(2 downto 0); 8 led: out std_logic_vector(7 downto 0) 9 ); 10 11 end shifter_test; 12 13 architecture arch of shifter_test is 14 begin shift_unit: entity work.barrel_shifter(multi_stage_arch) 15 port map(a=>sw, amt=>btn, y=>led); 16 17 end arch;

S3.ucf ISE only allows the pin assignments of the existing top-level I/O ports. If unused pin assignments are not deleted, an error will occur. To override the default option as follows: Select the top-level HDL file; Right-click the Implement Design process, then select Process Properties... Check the Allow Unmatched LOC constraints option and click OK. After this configuration, you can use the default s3.ucf (sent via email) as long as the same I/O port names are used as in the top- level module.