Modelling of the Digital Systems What are the digital systems - PowerPoint PPT Presentation

Modelling of the Digital Systems

What are the digital systems (circuits)? • Digital systems are based on binary representation 0 or 1 • Performing function of the Boolean logic Required circuits Boolean operators (inv, nand, nor, or, and) • Enabling storing of information in registers Usually with the clock edge Registers implemented as flip-flops or latches

Boolean Algebra • Boolean values Different representations On/OFF – Vdd/Gnd True/False 1/0 • Boolean operators NOT AND OR • Examples A = 1 B = C AND 0 F = /(A+B*C) Z= (/A+B)*(A+/B) 3

Truth Tables • Listing of all possible values of inputs and respective outputs A not A 0 1 1 0 A B A or B 0 0 0 1 0 1 0 1 1 1 1 1 A XOR B ? 4

Rules of Boolean Algebra • Commutivity A + B = B + A A * B = B * A • Associativity A+ (B + C) = (A+B)+C A* (B * C) = (A*B)*C • Distributivity A*(B+C)=A*B+A*C • Basic Relationships A*1=A A+0=A A*0=0 A+1=1 A*A=A A+A=A A*/A=0 A+/A=1 5

Rules of Boolean Algebra • De Morgan’s Law /(A*B) = /A+/B /(A+B) = /A * /B • Shannon’s expansion theorem F(A,B,C,D,…)=(A+F(0,B,C,D,…))*(/A+F(1,B,C,D,…)) 6

Logic Gates • Logic Symbols Equivalent Circuit Representation 7 M. Zwolinski – Digital System Design with VHDL

MINTERM and MAXTERM • Minterm – Boolean AND function containing one instance of each variable • Maxterm – Boolean OR function containing one instance of each variable A B C Z 0 0 0 1 m0 0 0 1 1 m1 0 1 0 0 M2 0 1 1 0 M3 1 0 0 0 M4 1 0 1 1 m5 1 1 0 0 M6 1 1 1 1 m7 Z= m0 + m1 + m5 +m7 Z=M2 * M3 * M4 * M6 8

Logic Minimization • Function of a combinational logic circuit can be described by one or more Boolean expressions. We need optimal implementation of combinational logic! Karnaugh Maps 9 M. Zwolinski – Digital System Design with VHDL

Karnaugh map • Grouping patterns Circle the largest possible groups Avoid circles inside circles 10 M. Zwolinski – Digital System Design with VHDL

Number Codes • Digital representation in set of bits • Integers Base 2 – 101 2 hex – 7AF 16 Two’s complement -6 = inverting 0110 + 1 = 1010 • Fixed-point numbers 6.25 = 110.01 The point is implicitly stored by knowing the position in advance • Floating-point numbers S- sign bit, e – exponent, m – mantisa (-1) s X 1.m X 2 e 11

Hardware Desciption Languages • Used to describe digital systems Different levels of representation: behavioural, structural • Imperative languages C, Basic, Assembler • HDL needs to enable concurrent execution of the statements Why? Concurrent execution • Example languages VHDL, Verilog

Combinational Code using VHDL • Combinational logic is stateless Changes in inputs immediately propagate to outputs In simulator this is however delta cycle delay • Entities and architectures Basic structures of VHDL Entity – Symbol (outer view of the block) Architecture - Implementation entity and2 is port (a, b : in BIT; c: out BIT); end entity and2; architecture struc of And2 is begin c <= a and b; 13 end architecture struc;

Handling more complex examples A B C Z 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 Use K-map to get result ! entity comb_function is port (a, b, c : in BIT; z: out BIT); end entity comb_function; architecture expression of comb_function is begin z <= (not a and b) or (a and c); end architecture expression; Why parentheses? 14 M. Zwolinski – Digital System Design with VHDL

Hierarchy architecture netlist2 of comb_function is component And2 is port (x, y : in BIT; z: out BIT); end component And2; component Or2 is port (x, y : in BIT; z: out BIT); end component Or2; component Not1 is port (x : in BIT; z: out BIT); end component Not1; signal p, q, r : BIT; begin g1: Not1 port map (a, p); g2: And2 port map (p, b, q); g3: And2 port map (a, c, r); g4: Or2 port map (q, r, z); end architecture netlist; 15 M. Zwolinski – Digital System Design with VHDL

Timing • Timing Diagram Boolean gates require some time for propagation In reality circuits and wires have intrinsic delay Usually when modeling in VHDL it is not required to handle the timing In some specific cases is however this recommended Sole combinational logic, race conditions, hazards 16 M. Zwolinski – Digital System Design with VHDL

Signal Assignments Z <= x and y; Several ways of modelling delay in VHDL Intertial delay Z <= x after 4 ns; Pulses shorter then 4 ns will be suppressed! Transport delay Z <= transport x after 4 ns; The assignments could be complex Z <= x and y after 4 ns; 17 M. Zwolinski – Digital System Design with VHDL

Testbenches We want to evaluate correctness of our model Usual way is simulation -> we need stimuli file We have to define a testbench which reads the stimuli, applies this to DUT and checks the results entity TestAnd2 is end entity TestAnd2; architecture io of TestAnd2 is signal a,b,c : BIT; begin g1: entity WORK.And2(ex2) port map (x=>a, y=>b, z=>c); a<= '0', '1' after 100 NS; b<= '0', '1' after 150 NS; end architecture io; 18 M. Zwolinski – Digital System Design with VHDL

Multi-valued Logic • Example - Three-State Buffer • We can define the types with different values type tri is (‘0’,’1’,’Z’); The signal can be then defined as Signal a, b, c: tri; • How to use tri same as bit signals? For example how to calculate: B<= a and c after 5 ns; • Defining the function AND 0 1 Z 0 0 0 0 1 0 1 1 Z 0 1 Z 19

Standard Logic Type • Normally the logic implemented in hardware is modelled with more than binary values (‘0’ and ‘1’) ‘Z’ – high impedance ‘L’ – weak 0 ‘H’ – weak 1 ‘U’ – undefined ‘X’ – strong unknown ‘W’ – weak unknown ‘ - ’ – don’t care type std_ulogic is (‘U’,’X’,’0’,’1’,’Z’,’W’,’L’,’H’,’ - ’); How AND truth table for std_ulogic could be defined? subtype std_logic is resolved std_ulogic; Standard types and functions are organized in a package We have to use them from the library library IEEE; use IEEE.std_logic_1164.all; 20

Latches • Difference latch / flip-flop? Example RS Latch S R Q /Q 0 0 1 1 0 1 0 1 1 0 1 0 1 1 Q /Q 21 M. Zwolinski – Digital System Design with VHDL

VHDL Model of RS-Latch library IEEE; use IEEE.std_logic_1164.all; entity SR_latch1 is port (S, R : in std_logic; Q, Qbar : buffer std_logic); end entity SR_latch1; architecture dataflow of SR_latch1 is begin Q <= '1' when R = '0' else '0' when S = '0' else Q; Qbar <= '1' when S = '0' else '0' when R = '0' else Qbar; end architecture dataflow; 22 M. Zwolinski – Digital System Design with VHDL

Design of D-Latch entity dlatch is port (d,en: in std_logic; d q q: out std_logic); end dlatch; en architecture struc of dlatch is begin process (en) begin if en='1' then q<=d; end if; end process; end struc; 23

Design of D-Flip-flop entity dff is port (d,clk: in std_logic; d q q: out std_logic); end dff; clk architecture struc of dff is begin process (clk) begin if clk='1' and clk’event then q<=d; end if; end process; end struc; 24

Design of D-Flip-flop with asynchronous Reset entity dff_r is port (d,clk,reset: in std_logic; d q q: out std_logic); end dff_r; reset architecture struc of dff_r is clk begin process (clk, reset) begin if reset=‘1' then q<=‘0’; elsif clk='1' and clk’event then q<=d; end if; end process; end struc; 25

Master-Slave Flip-Flop Figure source: Wikipedia

Design of D-Flip-flop with asynchronous Set and Reset entity dff_rs is port (d,clk,setn, resetn: in std_logic; d q q: out std_logic); setn end dff_rs; resetn architecture struc of dff_rs is clk begin process (clk, setn, resetn) begin if resetn=‘0' then q<=‘0’; Observe the polarity elsif setn=‘0' then of the control q<=‘1’; signals! elsif clk='1' and clk’event then q<=d; end if; end process; end struc; 27

Design of D-Flip-flop with synchronous Reset/Set entity dff_sr is port (d,clk,reset: in std_logic; d q q: out std_logic); end dff_sr; reset architecture struc of dff_sr is clk begin process (clk) begin if clk='1' and clk’event then if reset=‘1' then q<=‘0’; else q<=d; end if; end if; end process; end struc; 28

Timing and Logic checks Checking metastability as one type of timing check assert condition report message severity level; Severity level: NOTE, WARNING, ERROR, FAILURE library IEEE; use IEEE.std_logic_1164.all; entity D_FF is generic (Setup, Hold: TIME := 3 ns); port (D, Clk, Set, Reset: in std_logic; Q : out std_logic); begin assert (not(Clk ='1' and Clk'EVENT and not D'STABLE(Setup))) source: www.eet.com report "Setup time violation" severity WARNING; assert (not(Clk ='1' and D'EVENT and not Clk'STABLE(Hold))) report "Hold time violation" severity WARNING; end entity D_FF; architecture behavioural of D_FF is …. 29 M. Zwolinski – Digital System Design with VHDL