CENG 342 Digital Systems Routing with a Process Larry Pyeatt - PowerPoint PPT Presentation

CENG 342 – Digital Systems Routing with a Process Larry Pyeatt SDSM&T

Process Statements inside a process are written as if they will be executed sequentially . The process is actually a concurrent statement (or set of concurrent statements). For synthesis, two main purposes: Describe routing structures with if and case statements Construct templates for memory elements (Chapter 4) 1 process(b, c) 2 begin a <=b and c; 3 a <=c; 4 5 end process; The items in the parentheses ( b , and c ) are the sensitivity list . Each time one of them changes, the process runs. For a combinational circuit, all the input signals should be included in the sensitivity list. When a signal is assigned multiple times inside a process, only the last one takes effect.

Routing circuit with if statements if statement syntax: 1 if boolean1 then sequental_statement(s); 2 3 elsif boolean2 then sequential_statement(s); 4 5 ... 6 else sequential_statement(s); 7 8 end if;

Priority encoder (3 rd approach) r 4 r 3 r 2 r 1 f 2 f 1 f 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 - 0 1 0 0 1 - - 0 1 1 1 - - - 1 0 0 30 architecture if_arch of prio_encoder is 31 begin 32 process(r) 33 begin 34 if (r(4)=’1’) then 35 pcode <= "100"; 36 elsif (r(3)=’1’)then 37 pcode <= "011"; 38 elsif (r(2)=’1’)then 39 pcode <= "010"; elsif (r(1)=’1’)then 40 pcode <= "001"; 41 else 42 pcode <= "000"; 43 end if; 44 end process; 45 46 end if_arch;

Binary Decoder (3 rd approach) en a 1 a 0 Q 0 Q 1 Q 2 Q 3 0 - - 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 33 architecture if_arch of decoder_2_4 is 34 begin 35 process(en,a) 36 begin 37 if (en=’0’) then 38 y <= "0000"; 39 elsif (a="00") then 40 y <= "0001"; 41 elsif (a="01")then 42 y <= "0010"; elsif (a="10")then 43 y <= "0100"; 44 else 45 y <= "1000"; 46 end if; 47 end process; 48 49 end if_arch;

Routing circuit with case statements case statement syntax: 1 case sel is when choice(s) => 2 sequential_statement(s); 3 when choice(s) => 4 sequential_statement(s); 5 ... 6 when others 7 sequential_statement(s); 8 9 end case Multiple choices are separated by the pipe ( | ) character.

Priority encoder (4 th approach) r 4 r 3 r 2 r 1 f 2 f 1 f 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 - 0 1 0 0 1 - - 0 1 1 1 - - - 1 0 0 48 architecture case_arch of prio_encoder is 49 begin process(r) 50 begin 51 case r is 52 when "1000"|"1001"|"1010"|"1011"| 53 "1100"|"1101"|"1110"|"1111" => 54 pcode <= "100"; 55 when "0100"|"0101"|"0110"|"0111" => 56 pcode <= "011"; 57 when "0010"|"0011" => 58 pcode <= "010"; 59 when "0001" => 60 61 pcode <= "001"; 62 when others => 63 pcode <= "000"; 64 end case; 65 end process; 66 end case_arch;

Binary Decoder (4 th approach) en a 1 a 0 Q 0 Q 1 Q 2 Q 3 0 - - 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 51 architecture case_arch of decoder_2_4 is 52 signal s: std_logic_vector(2 downto 0); 53 begin 54 s <= en & a; 55 process(s) 56 begin case s is 57 when "000"|"001"|"010"|"011" => 58 y <= "0000"; 59 when "100" => 60 y <= "0001"; 61 when "101" => 62 y <= "0010"; 63 when "110" => 64 y <= "0100"; 65 when others => 66 y <= "1000"; 67 end case; 68 end process; 69 70 end case_arch;

Comparisons The if and case statements are equivalent to conditional signal assignment and selected signal assignment, respectively. However, if and case are more flexible and sometimes more efficient. Example: sort the values of two inputs and route them to the large and small outputs 1 -- Two greater-than comparators are needed to synthesize the 2 -- following using conditional signal assignment Large <= a when a>b else b; 3 Small <= b when a>b else a; 4 1 -- One greater-than comparator is needed to synthesize the 2 -- circuit using a process 3 -- note: process construct is required, but omitted here 4 if a>b then large <=a; 5 small <=b; 6 else 7 large <=b; 8 small <=a; 9 end if ; 10

Comparisons Example: find the maximal value of three inputs 1 process(a, b, c) 2 begin if (a>b) then 3 if (a>c) then 4 max <= a; 5 else 6 1 max <= a when ((a>b) and (a>c)) else max <= c; 7 c when (a>b) else end if 2 8 b when (b>c) else else 3 9 a; if (b>c) then 4 10 max <= b; 11 else 12 max <= c; 13 end if; 14 end if; 15 16 end process;

Rules for Processes Good coding habits: Include all input signals in the sensitivity list; Include the else branch in an if statement; Assign a value to every signal in every branch: VHDL standard specifies a signal keeps its previous value if it is not assigned in a process; Example: VERY GOOD! OK NOT GOOD! Assign defaults Process should run and minimize 1 process (a, b) when b changes, conditional bodies 2 begin and set values if (a>b) then 3 on all signals. gt <=’1’; 4 1 process (a, b) eq <=’0’; 5 2 begin process (a) 1 elsif (a=b) then 6 gt <=’0’; 3 begin 2 gt <=’0’; 7 eq <=’0’; 4 if (a>b) then 3 eq <=’1’; 8 if (a>b) then 5 gt <=’1’; 4 else 9 gt <=’1’; 6 elsif (a=b) then 5 gt <=’0’; 10 elsif (a=b) then 7 eq <=’1’; 6 eq <=’0’; 11 eq <=’1’; 8 end if; 7 end if; 12 end if; 9 end process; 8 13 end process; 10 end process;