CENG 342 Digital Systems Introduction to VHDL Larry Pyeatt - PowerPoint PPT Presentation

CENG 342 – Digital Systems Introduction to VHDL Larry Pyeatt SDSM&T

Overview VHDL is a popular language for describing digital hardware and widely used by industry worldwide VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language VHDL is initially supported by DoD, then transferred to IEEE IEEE has revised the standard several times Versions of VHDL: IEEE-1076 1987 IEEE-1076 1993 (adopted in the textbook) IEEE-1076 2000 (minor changes) IEEE-1076 2002 (minor changes) IEEE-1076 2008 VHDL vs. Verilog

1-bit Comparator Truth Table: VHDL: i 1 i 0 eq 1 library ieee; 0 0 1 2 use ieee.std_logic_1164.all; 3 0 1 0 4 entity eq1 is 1 0 0 port( 5 i0, i1: in std_logic; 6 1 1 1 eq: out std_logic 7 Logical function: ); 8 9 end eq1; eq = i 1 i 0 + i 1 i 0 10 11 architecture sop_arch of eq1 is signal p0, p1: std_logic; 12 Graphical representation: 13 begin -- sum of two product terms 14 eq <= p0 or p1; 15 i 0 -- product terms i 0 16 p0 <= (not i0) and (not i1); 17 i 0 i 1 18 p1 <= i0 and i1; i 1 i 1 19 end sop_arch; i 0 i 1 + i 0 i 1 i 0 i 1

Fundamentals of VHDL VHDL syntax is similar to Pascal, Modula 2, Algol, and Ada. Case insensitive: AndGate, andgate, andGate . . . Free formatting: spaces and blank lines can be inserted freely, but it is good practice to make the code clear and readable. Comments: start with -- and any following text in the same line is ignored. Rules of Names (identifier): Use only letters ( a-z or A-Z ), digits ( 0-9 ) and underscore( _ ); Must start with a letter. Do not use two or more consecutive underscores ( __ ) within a name All names and labels within a given entity and architecture must be unique Examples: Two_And_Gate , Gate1_and_gate2 . . .

Example 1 library ieee; Include libraries. 2 use ieee.std_logic_1164.all; 3 4 entity eq1 is To make programming and maintenance port( 5 easier, the file name should be the same i0, i1: in std_logic; 6 as the entity name. This file is eq1.vhdl eq: out std_logic 7 An entity declaration defines the inputs ); 8 and outputs of an object. 9 end eq1; 10 11 architecture sop_arch of eq1 is An entity may have multiple implemen- signal p0, p1: std_logic; 12 tations. Each implementation is an “ar- 13 begin chitecture”. -- sum of two product terms 14 eq <= p0 or p1; 15 -- product terms 16 p0 <= (not i0) and (not i1); 17 p1 <= i0 and i1; 18 19 end sop_arch;

Data Types and Operators VHDL is a strongly typed language, and allows new data types to be defined. We need a set of data types suitable for synthesis: std_logic is defined in a the IEEE Std 1164 library. To access it, you begin your file with: 1 library ieee; 2 Use ieee.std_logic_1164.all; The definition provided by the library is as follows: 1 type std_logic is ( ’U’, -- Uninitialized ’X’, -- Forcing Unknown 2 ’0’, -- Forcing 0 3 ’1’, -- Forcing 1 4 ’Z’, -- High Impedance 5 ’W’, -- Weak Unknown 6 ’L’, -- Weak 0 7 ’H’, -- Weak 1 8 ’-’ ); -- Don’t Care 9 This is an example of an enumerated type . Three of the values 0 , 1 , and Z , can be synthesized (used in actual circuits). The values U and X may be used in simulation. The other four values are not used in this class.

Data Types and Operators – Continued Array of logic values The std_logic_vector data type is defined as an array with elements of std_logic . Example: a: in std_logic_vector(7 downto 0) 1 Defines an array of eight elements a(7), a(6), ...a(0) . Logical Operators: not , and , or , xor , nor , xnor , and nand , are defined over the std_logic and std_logic_vector data types. These operators have equal precedence, so you must use parenthesis to specify the desired order of evaluation. For example: (A and B) or (C and D)

Entities An entity declaration defines the signals that connect this object to other objects. Syntax: 1 entity entity_name is port ( 2 port_name_list : port_mode data_type; 3 port_name_list : port_mode data_type; 4 ............. 5 port_name_list : port_mode data_type; 6 port_name_list : port_mode data_type 7 ); 8 9 end entity_name; Note: no semicolon after the last port declaration, the last semicolon is located outside the parenthesis. Example: 4 entity eq1 is port( 5 i0, i1: in std_logic; 6 eq: out std_logic 7 ); 8 9 end eq1;

Architectures An architecture describes the implementation/operation of the circuit Each entity can have multiple architectures Syntax: 1 architecture architecture_name of entity_name is 2 declarations -- (optional) 3 begin -- code 4 5 end architecture_name; Example: 11 architecture sop_arch of eq1 is signal p0, p1: std_logic; 12 13 begin -- sum of two product terms 14 eq <= p0 or p1; 15 -- product terms 16 p0 <= (not i0) and (not i1); 17 p1 <= i0 and i1; 18 19 end sop_arch; Note that the signals do not have to be assigned values in sequential order. This is declarative programming.

Programming Paradigms Note that the signals do not have to be assigned values in sequential order. Most computer programming languages fall into one of two paradigms: Imperative programming focuses on each step that must be performed, and defines control flow as statements that change a program state. The order of the statements is important. Examples: C, C++, Pascal, Assembly, VHDL processes (covered tomorrow). Declarative programming focuses on the logic of the computation, without describing the control flow. The order in which the statements are given is not important. Examples: Prolog, MetaPost, SQL, Analytica, VHDL