SoC Design SoC Design : Designing with FPGAs Designing with FPGAs - PowerPoint PPT Presentation

SoC Design SoC Design : Designing with FPGAs Designing with FPGAs es g es g g w t g w t G s G s Lecture 5: Lecture ectu e 5: ectu e Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology

Outline Outline � Designing for High Speed Designing for High Speed � Designing for Signal Integrity � Designing for Signal Integrity Designing for Signal Integrity Designing for Signal Integrity � Designing for Low Power Designing for Low Power � Designing for Security � Designing for Security Designing for Security Designing for Security � Asynchronous Design Issues Asynchronous Design Issues Sharif University of Technology Designing with FPGAs Page 2

Designing for High Speed Designing for High Speed 1. Provide high Provide high- -level floor planning level floor planning 1. � Intelligent pin assignment � Intelligent pin assignment Intelligent pin assignment Intelligent pin assignment – prevents routing congestion and poor performance prevents routing congestion and poor performance � Natural structure: Natural structure: – Data flows horizontally, Control flows vertically Data flows horizontally, Control flows vertically – Vertical adders and counters, carry going upwards Vertical adders and counters, carry going upwards � Pick the best I/O standard � Pick the best I/O standard Pick the best I/O standard Pick the best I/O standard Place & route tool should not do all your work Place & route tool should not do all your work Place & route tool should not do all your work Place & route tool should not do all your work Sharif University of Technology Designing with FPGAs Page 3

Designing for High Speed (cont’d) Designing for High Speed (cont’d) 2. Design synchronously, use global clocks Design synchronously, use global clocks 2. � � Up to 16 Up to Up to 16 Up to 16 Global Clocks are available 16 Global Clocks are available Global Clocks are available Global Clocks are available Very low skew on these clock nets Very low skew on these clock nets – � DLL (Delay DLL (Delay- -Locked Loop) eliminates Locked Loop) eliminates clock distribution delay clock distribution delay Inside the chip, or even on the pc Inside the chip, or even on the pc- -board board – � Do not gate the clock, use CE instead Do not gate the clock, use CE instead But you may need clock gating for lowest power But you may need clock gating for lowest power But you may need clock gating for lowest power But you may need clock gating for lowest power – Virtex Virtex- -II has glitch II has glitch- -free clock gate and clock free clock gate and clock mux mux – � Use Carry for adders, counters and comparators Use Carry for adders, counters and comparators Superior speed, less logic, forces vertical orientation Superior speed, less logic, forces vertical orientation – � Use predefined cores Use predefined cores Have been tested and are guaranteed to work at speed Have been tested and are guaranteed to work at speed Have been tested and are guaranteed to work at speed Have been tested and are guaranteed to work at speed – Sharif University of Technology Designing with FPGAs Page 4

Designing for High Speed (cont’d) Designing for High Speed (cont’d) 3. Use local buffers to reduce clock skew Use local buffers to reduce clock skew 3. � � Global buffers are connected to dedicated routing Global buffers are connected to dedicated routing Global buffers are connected to dedicated routing Global buffers are connected to dedicated routing Global clock network is balanced to minimize skew Global clock network is balanced to minimize skew – � All Xilinx FPGAs have global buffers All Xilinx FPGAs have global buffers XC4000 XC 4000 and Spartan have and Spartan have 8 8 – Virtex Virtex and Spartan and Spartan- -II have II have 4 4 – Virtex Virtex- -II has II has 16 16 BUFGs with glitch BUFGs with glitch- g -free input free input mux p mux – � You can always use a BUFG symbol and the software will You can always use a BUFG symbol and the software will choose an appropriate buffer type choose an appropriate buffer type All All All major synthesis tools can infer global buffers onto clock signals All major synthesis tools can infer global buffers onto clock signals j j th th i t i t l l i f i f l b l b ff l b l b ff t t l l k i k i l l – that come from off that come from off- -chip chip Sharif University of Technology Designing with FPGAs Page 5

Designing for High Speed (cont’d) Designing for High Speed (cont’d) 4. Use timing constraints Use timing constraints 4. � � The implementation tools do NOT try to find the placement and The implementation tools do NOT try to find the placement and The implementation tools do NOT try to find the placement and The implementation tools do NOT try to find the placement and routing that achieves the fastest speed routing that achieves the fastest speed They just try to meet your performance expectations They just try to meet your performance expectations – � � YOU YOU must communicate your expectations YOU YOU must communicate your expectations t t i i t t t ti t ti Through Timing Constraints Through Timing Constraints – � Timing Constraints improve performance Timing Constraints improve performance g g p p p p By placing logic closer together and shortening the routing By placing logic closer together and shortening the routing – Timing constraints define your performance objectives Timing constraints define your performance objectives – � � Ti ht ti Tight timing constraints increases compile time Tight timing constraints increases compile time Ti ht ti i i t t i t i i t i il il ti ti � Unrealistic constraints causes the Flow Engine to stop Unrealistic constraints causes the Flow Engine to stop � Logic Level Timing Report tells whether constraints are Logic Level Timing Report tells whether constraints are realistic realistic Timing constraints are the best high Timing constraints are the best high- -level tool to achieve level tool to achieve guaranteed performance guaranteed performance guaranteed performance guaranteed performance Sharif University of Technology Designing with FPGAs Page 6

Designing for Signal Integrity Designing for Signal Integrity 1. Devices need good Devices need good Vcc Vcc bypassing bypassing 1. � Bypass capacitor is the only source of dynamic current � Bypass capacitor is the only source of dynamic current Bypass capacitor is the only source of dynamic current Bypass capacitor is the only source of dynamic current 2. User needs understanding of transmission line effects User needs understanding of transmission line effects 2. � Characteristic impedance, reflections, Characteristic impedance, reflections, dV p dV/dt dt � Series termination, parallel termination Series termination, parallel termination 3. Decouple power supply Decouple power supply 3. � CMOS current is dynamic CMOS current is dynamic – Icc Icc current spike on every active clock edge current spike on every active clock edge � Peak current can be � Peak current can be Peak current can be 5x the average current Peak current can be 5x the average current x the average current x the average current – Instantaneous current peaks only supplied by decoupling capacitors Instantaneous current peaks only supplied by decoupling capacitors 1 μ F ceramic chip capacitor per � Use one Use one 0 0. .1 F ceramic chip capacitor per Vcc Vcc pin pin Sharif University of Technology Designing with FPGAs Page 7

Designing for Signal Integrity (cont’d) Designing for Signal Integrity (cont’d) 4. Use SLOW attribute where available Use SLOW attribute where available 4. � � Increases transition time Increases transition time Increases transition time Increases transition time especially when driving transmission lines especially when driving transmission lines – � Reduce fan- Reduce fan -out and load capacitance out and load capacitance � Add virtual Add virtual ground ground Ground output pin inside and outside, give it max strength Ground output pin inside and outside, give it max strength – 5. Test for performance and reliability Test for performance and reliability Test for performance and reliability Test for performance and reliability 5 5. � Manipulate circuit speed for testing purposes: Manipulate circuit speed for testing purposes: Hot and low Hot and low Vcc Vcc = slow operation = slow operation p – Cold and high Vcc Cold and high Vcc = fast operation = fast operation – � If it fails hot: insufficient speed If it fails hot: insufficient speed U Use a faster speed grade Use a faster speed grade U f f t t d d d d – – Modify the design, add pipelining Modify the design, add pipelining Sharif University of Technology Designing with FPGAs Page 8