SoC Design SoC Design g L Lecture Lecture 6: IP Cores 6 IP C : - PowerPoint PPT Presentation

SoC Design SoC Design g L Lecture Lecture 6: IP Cores 6 IP C : IP Cores IP C Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology

IP Core IP Core � Intellectual Property (IP) core: predesigned and pre Intellectual Property (IP) core: predesigned and pre- - verified modules used in ASIC/SOC designs. verified modules used in ASIC/SOC designs. g � A Virtual Components (VC) with well A Virtual Components (VC) with well- -defined functions, usage defined functions, usage method, and tools to support its usage. method, and tools to support its usage. � Benefits: Benefits: � Reduce time Reduce time- -to to- -market by market by means of design reuse means of design reuse f d f d i i � Reduce the possibility of Reduce the possibility of failure failure � Drawback: Drawback: � Designing an IP block Designing an IP block generally requires greater generally requires greater effort and higher cost effort and higher cost Resources versus Number of Uses Resources versus Number of Uses Sharif University of Technology IP Cores Page 2

Design Reuse Design Reuse g � Design with reuse can have a significant impact: Design with reuse can have a significant impact: � IP blocks should have well � IP blocks should have well IP blocks should have well-defined interfaces IP blocks should have well defined interfaces. defined interfaces defined interfaces. Sharif University of Technology IP Cores Page 3

What Is an IP Core? What Is an IP Core? � At least At least 5 5K gates, K gates, � Pre � Pre Pre-designed Pre-designed, designed designed, � Pre Pre- -verified, verified, � Re � Re Re-usable, Re-usable usable usable, � H/W S/W Functional Blocks. H/W S/W Functional Blocks. � Examples: � Examples: Examples: Examples: � Processor: ARM Processor: ARM7 7, ARM , ARM9 9, and ARM , and ARM10 10, ARC, Leon. , ARC, Leon. � DSP cores: TI TMS DSP cores: TI TMS320 320C C54 54X, Pine, Oak, MPEG X, Pine, Oak, MPEG- , , , , , , -2, MPEG , MPEG- , -4 4. . � Mixed signal: ADCs, DACs, Audio Mixed signal: ADCs, DACs, Audio Codecs Codecs, PLLs, , PLLs, OpAmps OpAmps. . � Encryption: Encryption: PKuP PKuP, DES. , DES. � I/Os: PCI, USB, I/Os: PCI, USB, 1394 1394, , 1284 1284, E , E- -IDE, IrDA. IDE, IrDA. � Miscellaneous: UARTs, DRAM Controller, Timers, Interrupt Miscellaneous: UARTs, DRAM Controller, Timers, Interrupt Controller DMA Controller Controller DMA Controller Controller, DMA Controller. Controller, DMA Controller. Sharif University of Technology IP Cores Page 4

Environment Environment � Core Providers: Core Providers: � What do I need to deliver a “product” while protecting technology � What do I need to deliver a product while protecting technology What do I need to deliver a “product” while protecting technology What do I need to deliver a product while protecting technology and avoiding downstream liabilities? and avoiding downstream liabilities? Core Users: Core Users: � � How do I effectively use external components? How do I effectively use external components? � How do I guarantee that the end product works? How do I guarantee that the end product works? Foundry Services. Foundry Services. F F d d S S i i � Standards Folks: Standards Folks: � � Define interfaces/standards/methods to maximize mix Define interfaces/standards/methods to maximize mix- D fi D fi i t i t f f / t / t d d d / d / th d t th d t i i i i i i -and and-match. d match. t h t h The The Legals Legals: : � � Clarify responsibilities and liabilities � Clarify responsibilities and liabilities. Clarify responsibilities and liabilities Clarify responsibilities and liabilities. Sharif University of Technology IP Cores Page 5

Advantages of Core Advantages of Core- -Based Design Based Design � Allows to functionally verify each complex function block Allows to functionally verify each complex function block with post with post- -layout timing as soon as RTL design and layout timing as soon as RTL design and simulation are completed. simulation are completed. � Makes the back Makes the back- -end physical data available at the front end physical data available at the front- - end of the design cycle, where it can influence algorithm end of the design cycle where it can influence algorithm end of the design cycle, where it can influence algorithm end of the design cycle where it can influence algorithm and/ or architecture trade and/ or architecture trade- -offs (Coupling physical and offs (Coupling physical and system design). system design). Bridging the gap between front end and back end � � Bridging the gap between front end and back end virtually eliminates timing uncertainty virtually eliminates timing uncertainty � It is possible to use post It i It i It is possible to use post-layout ibl ibl t t t t l layout parasitics l t t parasitics. iti iti . Results: Results: � � More time for block design (block � More time for block design (block More time for block design (block level timing convergence), but More time for block design (block- level timing convergence) but level timing convergence) but level timing convergence), but net savings net savings 25 25% to % to 30 30% on the overall timing convergence (chip % on the overall timing convergence (chip- - level) and gate level) and gate- -level debugging. level debugging. Sharif University of Technology IP Cores Page 6

Marketplace Experiences Marketplace Experiences � Small IP: Small IP: � Blocks requiring � Blocks requiring Blocks requiring 1 2 Blocks requiring 1-2 staff years to design are priced at 2 staff years to design are priced at staff years to design are priced at 1/3 staff years to design are priced at 1/3 of the 3 of the of the of the development cost. development cost. � Buyers are skeptical about the value and often prefer to do these Buyers are skeptical about the value and often prefer to do these in-house. in in house in house. house � Medium IP: Medium IP: � Blocks requiring � Blocks requiring Blocks requiring 5-10 Blocks requiring 5-10 10 staff years are profitable for both seller and 10 staff years are profitable for both seller and staff years are profitable for both seller and staff years are profitable for both seller and buyer. buyer. � STAR IP: STAR IP: � Blocks requiring Blocks requiring 100 100+ staff years to design (like ARM, MIPS ) + staff years to design (like ARM, MIPS ) have become bestsellers and come with lots of support. have become bestsellers and come with lots of support. Sharif University of Technology IP Cores Page 7

Core Types Core Types- - Soft Cores Soft Cores � Soft cores (“code”): Soft cores (“code”): � RTL (or higher level) description, to provide functional descriptions of RTL (or higher level) description, to provide functional descriptions of IP IP IPs. IPs. � Maximum flexibility and Maximum flexibility and reconfigurability reconfigurability, i.e., can be changed to suit an , i.e., can be changed to suit an application. application. � Must be synthesized, optimized, and verified by user before integration Must be synthesized, optimized, and verified by user before integration into designs. into designs. – quality of a soft IP depends on the effort needed in the IP quality of a soft IP depends on the effort needed in the IP integration stage. integration stage. � Technology independent: may be re Technology independent: may be re- -synthesized across processes. synthesized across processes. � Significant IP protection risks. Significant IP protection risks. g g p p � May May include include macroblocks macroblocks or or megacells megacells, typically designed at the , typically designed at the physical level. physical level. – Soft core provider supplies behavioral or functional models for the Soft core provider supplies behavioral or functional models for the Soft core provider supplies behavioral or functional models for the Soft core provider supplies behavioral or functional models for the megacells megacells used in the core (for simulating the core at high levels). used in the core (for simulating the core at high levels). – The core user has to implement the technology The core user has to implement the technology- -dependent dependent megacells megacells—a potentially challenging task. g a potentially challenging task. p p y y g g g g Sharif University of Technology IP Cores Page 8