IPBus framework on the zcu102 build instructions updated on 27 July - PowerPoint PPT Presentation

IPBus framework on the zcu102 — build instructions updated on 27 July 2019 — Kristian Harder (RAL), 18 Oct 2018 1

IPbus concept IPbus protocol: simple packet-based control protocol for reading and modifying memory-mapped resources within FPGA-based devices which have a virtual A32/D32 bus. IPbus suite of software and firmware implement a reliable high-performance control link for electronics, based on the IPbus protocol. Runs with various transport layers, mainly: UDP on GBit ethernet (with added reliability mechanism) PCIe Has also been used across TCP/IP and SPI links. Open source license, active development team see https://ipbus.web.cern.ch/ipbus/ for full documentation Kristian Harder (RAL), 18 Oct 2018 2

IPbus software suite uhal (pronounce “microHAL”): Hardware Access Library providing an end-user C++/Python API for IPbus reads, writes and RMW (read-modify-write) transactions Controlhub: adds reliability mechanism for UDP and multi-client management see https://ipbus.web.cern.ch/ipbus/ for full documentation Kristian Harder (RAL), 18 Oct 2018 3

IPbus address table can include address tables files representing firmware modules can define names for individual bit ranges within 32 bit registers declares read and write permissions declares register types (FIFO, block RAM, plain register, ...) VHDL address decoder functions generated from xml address tables Kristian Harder (RAL), 18 Oct 2018 4

IPbus build system: ipbb supports and encourages modular firmware structure supports multiple svn/git repositories defines packages with hierarchies and dependencies enforces consistency between firmware IPbus register structure and xml address table for software batch-capable, supporting automated builds see https://ipbus.web.cern.ch/ipbus/ for full documentation Kristian Harder (RAL), 18 Oct 2018 5

the zcu102 dev board based on Zynq Ultrascale+, very well equipped, two HPC FMC slots Kristian Harder (RAL), 18 Oct 2018 6

step 1: set up build system mkdir zcu102 cd zcu102 git clone https://github.com/ipbus/ipbb cd ipbb git checkout -q tags/v0.5.0 source env.sh cd .. Kristian Harder (RAL), 18 Oct 2018 7

step 2: install firmware components # initialize a new build area ipbb init zcu102 cd zcu102 # add the core IPbus firmware source ipbb add git https://github.com/ipbus/ipbus-firmware This repository is public, i.e. you should not need a CERN account to use this. Please let me know if you have problems accessing the files! The zcu102 example is part of the main IPbus repository, but your own design should go into a separate location. Kristian Harder (RAL), 18 Oct 2018 8

step 3: build # create a directory for this project within the build area ipbb proj create vivado zcu102-example \ ipbus-firmware:projects/example/ \ -t top zcu102 basex.dep cd proj/zcu102-example # set up your preferred Vivado - site specific location source /opt/ppd/tools/xilinx/Vivado/2018.3/settings64.sh # create Vivado project file and regenerate all IP cores - this takes a while ipbb vivado project # now either run vivado top/top.xpr # or use the following commands for script-based build and packaging ipbb vivado synth -j4 impl -j4 ipbb vivado package The package command creates a tar archive with bit file and associated xml address table Kristian Harder (RAL), 18 Oct 2018 9

step 4: use Easiest test: run python interactively, try the following: import uhal hw=uhal.getDevice(”zcu102”,”ipbusudp-2.0://192.168.200.16:50001”, ”file://ipbus example.xml”) hw.getNode(”reg”).write(0x12345678) hw.dispatch() reg=hw.getNode(”reg”).read() hw.dispatch() print hex(reg) NB: ipbus example.xml is located in the ipbus-firmware repository, components/ipbus util/addr table/ipbus example.xml Kristian Harder (RAL), 18 Oct 2018 10

summary Very straightforward framework available for use: IPbus firmware uhal software framework ipbb modular build system Used in many experiments already. Active support and development by RAL and others. Typical application in CMS trigger upgrade project: algorithm tests on processing boards with optical I/O, big FPGA configure and monitor algorithm (and other parameters) by IPbus load simulated data into input link buffers with IPbus play actual algorithm read output data from output link buffers with IPbus Kristian Harder (RAL), 18 Oct 2018 11