Research on Ultra Low Power SoC for Media Processing SoC for Media Processing August 1, 2011 g , S t Satoshi Goto hi G t Waseda University y ISLPED2011 1
Multimedia Applications in Ambient Multimedia Applications in Ambient Society Society Society Society TV conference TV conference Surveillance/medical care Surveillance/medical care Automotive Automotive • Security/privacy, recognition, record • Scene recognition / Scene recognition / • Ultra-low power, wireless Monitoring / Control • Information (figure, text) • Bi-directions display safe safe anytime anytime • Small frame delay y • Noise and vibration Noise and vibration • Wide range capture (fish eye camera) Mobile/Portable Mobile/Portable Mobile/Portable Mobile/Portable anywhere an anywhere an here here comfortable comfortable comfortable comfortable Video compression Video compression Home entertainment Home entertainment + Network • A battery drive (low power) • HDTV or Super HDTV (High quality) Security Security • Wireless (error free) • Wireless (error free) • Recording (High compression) • Recording (High compression) • New function (Fast • Various contents (a sport, news, a Recognition forwarding, etc) movie, animation, --) ：
Media Processing SoC and Research Area Digital signal processing Med Med M Media enc Media enc dia / Envi dia / Envi Recogni Recogni Pre/Po Pre/Po Sensor Sensor Error Error Netw Netw RF RF En En ost proces ost proces work proto work proto ncryption ncryption ition/Synt ition/Synt ironment ironment coding/de coding/de r collectio r collectio r Display Display or or tal Inform tal Inform on on ssing ssing thesis thesis ecoding ecoding ocol ocol R RF RF y/Actuato y/Actuato wire/ wire/ wireless wireless mation mation or or UWB UWB object tracking object tracking public key public key LDPC LDPC coordinate coordinate / recognition / recognition 11a/b/g/n 11a/b/g/n H.264 H.264 private key private key translation translation character character ad hoc ad hoc JPEG2000 JPEG2000 turbo turbo recognition recognition interpolation interpolation interpolation interpolation 10G 10G baseT 10G baseT 10G baseT baseT stream stream t image i image i non- non -standard standard RS RS cipher cipher analysis analysis digital filter digital filter codec codec 4G 4G CG CG Challenge: Challenge: How do we realize Ultra low-power consumption chip? 3
Opportunities for power reduction reduction Silicon System Register Gate Transistor Algorithm Level Level Transfer Level Transfer Level Level Level Level Level Level L l Power Reduction >70% 50-70% 15-50% 5-15% 3-5% Precision Error >50% 50% 25 50% 25-50% 15 40% 15-40% 10-20% 10 20% 5-10% 5 10% Possible power reduction and observation accuracy of power consumption achieved at each abstraction level From ASIC/IC における消費電力管理 （ by Synopsys) おける消費電力管理 （ Optimizations at System , Algorithm and Register- transfer levels are important for Ultra-low power SoC ISLPED2011 4
１ What is a low power design ? １． What is a low power design ? 2 Power reduction at System level 2. Power reduction at System level 3 Power reduction at Algorithm level 3. Power reduction at Algorithm level 4. Power reduction at RTL level 5. Power reduction examples by Chip 6. Product oriented activity ISLPED2011 5 7. Conclusions
Power Consumption f 2 2 P = α C V DD f ＋ I leak V DD Dynamic Power Dynamic Power Static Power Static Power α ： Operational rate p C ： Capacitance f f ： Clock frequency ∝ （ V DD－ V TH ） （ V V Cl k f ） V DD ： Power voltage V V TH ： Threshold voltage h h ld l I leak ： Leak current ISLPED2011 6
Reducing Power Consumption 2 ∑ ∑ ∑ ∑ P = P = αC V DD f αC V DD f ＋ ＋ I leak V DD I leak V DD Lower power voltage Less leakage current Less leakage current Turn off power Fine Process Device and low voltage Fine Process, Device and low voltage Power gating ISLPED2011 7
Reducing Power Consumption 2 ∑ ∑ ∑ ∑ P = P = αC V DD f αC V DD f ＋ ＋ I leak V DD I leak V DD （１） L （１） Lower Power voltage P lt （ 2 ） Reduced operational rate （３） Lower Clock frequency （３） L Cl k f （４） Turn off Clock ・ Parallel process 、 Pipeline Parallel process 、 Pipeline ・ Reduce the number of logic circuits ・ Reduce the number of computation Reduce the number of computation ・ Clock gating ASICON2009 8
Low Power Design g Signal Encode Cypher Application pp Process Recognition Recognition ECC ECC NW Protocol NW Protocol Decode Encription Algorithm Algorithm Low Power Algorithm Low Power Algorithm Task １ Task ２ Task ３ Task ４ Hetero Multi-core Execution Control Programmable Multi Implementation Low Power IP Core ASIP HW Processor Platform Low Power Design basic Technologies Clock GT Power GT RTL Floor Plan High Level Synth
Low Power Design Goal g Our Goal Our Goal 1/100 Signal Encode Cypher =1/5x1/10 1/5x1/10 Process Recognition Recognition ECC ECC NW Protocol NW Protocol Decode Encription x1/2 Low Power Algorithm Low Power Algorithm 1/5 1/5 Task １ Task ２ Task ３ Task ４ Hetero Multi-core Execution Control Programmable Multi 1/10 Low Power IP Core ASIP HW Processor 1/2 Low Power Design basic Technologies Clock GT Power GT Floor Plan High Level Synth
１ What is a low power design ? １． What is a low power design ? 2 Power reduction at System level 2. Power reduction at System level 3 Power reduction at Algorithm level 3. Power reduction at Algorithm level 4. Power reduction at RTL level 5. Power reduction examples by Chip 6. Product oriented activity ISLPED2011 11 7. Conclusions
Power Reduction at System Power Reduction at System Level Classification and I ntegration Classification – Classify media data into “Important part” and “Non- Important part” p p p p I ntegration – Error-Correcting Coding & Video Processing – Encryption & Video Processing → Reduce complexity by 25 ％～ 75 ％ 12
Power Reduction at System Level - Classification Video Compression （ ex. H.264 ex. H.264 ） General Media Information General Media Information Video Compression Motion Headder, quantization Others DCT coeff. DCT coeff. vector vector mtx etc mtx. etc Image Image Information Information Text Information Text Information （ Still image 10 Still image 10 （ 1000 Chars, 16KBits 1000 Chars, 16KBits ） pictures, 240Mbits) pictures, 240Mbits) • Data leaked • Data leaked • Part of data leaked • Part of data leaked ≠ Whole information leaked ≠ Whole image information leaked → Image information → Meaning leaked leaked • Partial error occurred • Partial error occured • Error occurred • Error occurred ≠ Whole information lost ≠ ≠ Whole image information lost ≠ → Information lost → whole image lost I f ti l t h l i l t h l f l h l f l I mportant I nformation I mportant I nformation Non-I mportant I nformation Non I mportant I nformation Decrease Cipher Strength High Cipher Strength Encryption （ 2000bit RSA AES ect ） （ 2000bit RSA, AES, ect ） depending on the importance depending on the importance Decrease error correcting High error correcting capability Encoding （ 10000bit LDPC code etc ） （ 10000bit LDPC code, etc ） capability depending on the capability depending on the importance 13
Power Reduction at System Level System Level Power Reduction at - Integration of Video Encoding and Error Integration of Video Encoding and Error- -Correcting Coding Correcting Coding - - Experiment for the Integration of Image Processing and Error Correcting Coding Error-Correcting Coding Classification of H.264 Video Data Non-important Important Coding Ratio Low High #Repetitions of #Repetitions of Large Small LDPC Code LDPC Code LDPC Code Long Short Length Computing Computing Large Small time 14
Classified Data(bit) Classified Data(bit) Partition A Partition B (Important) (Unimportant) foreman_qcif 21659 34657 football_qcif 22312 77581 salesman_qcif 13091 33167 container_qcif 6698 25036 ISLPED2011 15
Power Reduction at System Level - Integration of Video Encoding and Error-Correcting Coding - Experiment for Unequal ECC in Video Encoder 37 36 35 35 34 33 33 33 31 32 31 29 NOUEP 30 27 UEP1 29 UEP2 25 UEP3( 提案 ) 28 2.9 3 3.1 3.2 3.3 3.4 3 3.1 3.2 3.3 3.4 3.5 container Independent foreman Integrated Integrated Foreman Football Container Power 25.5% 25.4% 56.6% 16 Reduction
SASIMI 2009 SASIMI 2009 17 UEEC UEEC 38.0 １ Results for UEEC : ITC-CSCC 2010 ３ EQ 52.5 EQ Computation time PSNR Quality Video Vid
１ What is a low power design ? １． What is a low power design ? 2 Power reduction at System level 2. Power reduction at System level 3 Power reduction at Algorithm level 3. Power reduction at Algorithm level 4. Power reduction at RTL level 5. Power reduction examples by Chip 6. Product oriented activity ISLPED2011 18 7. Conclusions
Power Reduction at Algorithm L Level l Classification Region of Interest (ROI) based complexity reduction is Introduced Classification by inside ROI or outside ROI Classification by inside ROI or outside ROI ► video conference systems, etc 19 ISLPED2011
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