14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #13: Digital Comparators Digital Comparators Comparator : A circuit that compares two binary words and indicates whether they are equal Magnitude comparator : Interprets its inputs as signed or unsigned numbers and indicates their arithmetic relationship (greater or less than) 2 of 12 1
Example Comparator Use Devices are enabled by comparing a “device select” word with a predetermined “device ID” 3 of 12 Equality Comparators 1-bit comparator 1/4 74x86 1 A0 • Active-high output 3 DIFF 2 B0 (DIFF) asserted if the U1 inputs are different EQ_L 74x86 4-bit comparator 1 DIFF0 A0 3 2 B0 U1 • The DIFF output is 4 A1 DIFF1 asserted if any of the 6 5 B1 input pairs are different U1 DIFF 9 DIFF2 A2 8 10 B2 U1 EQ_L 12 A3 DIFF3 11 13 B3 U1 4 of 12 2
4-Bit Magnitude Comparator Two input numbers to compare, 4 bits each: A =A 3 A 2 A 1 A 0 ; B =B 3 B 2 B 1 B 0 Three outputs, reporting “greater than”, “less than”, and “equal”, respectively Compared Inputs Outputs A3, B3 A2, B2 A1, B1 A0, B0 “A > B” “A < B” “A = B” A3 > B3 x x x 1 0 1 A3 < B3 x x x 0 1 0 A3 = B3 A2 > B2 x x 1 0 0 A3 = B3 A2 < B2 x x 0 1 0 A3 = B3 A2 = B2 A1 > B1 x 1 0 0 A3 = B3 A2 = B2 A1 < B1 x 0 1 0 A3 = B3 A2 = B2 A1 = B1 A0 > B0 1 0 0 A3 = B3 A2 = B2 A1 = B1 A0 < B0 0 1 0 A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 0 A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 0 A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 1 Note “x” (don’t care) notation. 5 of 12 4-Bit Magnitude Comparator Input A =A 3 A 2 A 1 A 0 ; B =B 3 B 2 B 1 B 0 XNOR Case A = B : A 3 =B 3 , A 2 =B 2 , A 1 =B 1 , A 0 =B 0 A3 xi = (Ai Bi) = Ai·Bi + Ai ·Bi x3 XNOR = (Ai Bi) = (Ai·Bi + Ai ·Bi) B3 = (Ai +Bi)·(Ai+Bi ) = Ai ·Ai + Ai ·Bi + Ai·Bi + Bi·Bi = Ai·Bi + Ai ·Bi A2 x2 – Output : x3·x2·x1·x0 Case A > B : B2 – Output : (A<B) A3·B3 + x3·A2·B2 + x3·x2·A1·B1 + x3·x2·x1·A0·B0 A1 x1 Case A < B : – Output : B1 A3 ·B3 + x3·A2 ·B2 + x3·x2·A1 ·B1+ x3·x2·x1·A0 ·B0 A0 (A>B) x0 B0 (A=B) X (X Y) Y 6 of 12 3
Iterative Combinational Circuits General structure: n identical modules – For problems that can be solved by an iterative algorithm: 1. Set C 0 to its initial value and set i to 0 2. While i < n repeat: a) Use C i an PI i to determine the values of PO i and C i+1 b) Increment i a primary inputs cascading cascading PI 0 PI 1 PI n –1 input output PI PI PI C 0 C 1 C 2 C n –1 C n CI module CO CI module CO CI module CO PO PO PO boundary boundary inputs outputs PO 0 PO 1 PO n –1 primary outputs 7 of 12 An Iterative Comparator Circuit (a) module for one bit (a) X Y (b) complete circuit CMP – Comparing two n -bit values X and Y: 1. Set EQ 0 to 1 and set i to 0 EQO 2. While i < n repeat: EQI a) If EQ i is 1 and X i equals Y i , set EQ i+1 to 1 Else set EQ i+1 to 0 b) Increment i EQO = (A B) · EQI Slow because the cascading signals need time to “ripple” from left to right X0 Y0 X1 Y1 X2 Y2 X(N–1) Y(N–1) (b) X Y X Y X Y X Y CMP CMP CMP CMP EQ1 EQ2 EQ3 EQ(N–1) EQN 1 EQI EQO EQI EQO EQI EQO EQI EQO first input has to be 1 8 of 12 4
4-bit Comparator 74x85 Outputs: 74x85 – Greater-than output (AGTBOUT) 2 7 ALTBIN ALTBOUT – Less-than output (ALTBOUT) 3 6 AEQBOUT AEQBIN – Equal output (AEQBOUT) 4 5 AGTBIN AGTBOUT Cascading inputs: 10 A0 – AGTBIN, ALTBIN, AEQBIN 9 B0 Cascading inputs and the outputs are arranged 12 A1 in a 1-out-of-3 code, since normally exactly one 11 B1 input and output should be asserted 13 A2 14 B2 15 A3 1 B3 9 of 12 12-bit Comparator using 74x85s AGTBOUT = (A>B) + (A=B) · AGTBIN AGTBOUT = (A=B) · AEQBIN AGTBOUT = (A<B) + (A=B) · ALTBIN XNOR (A>B) = A3·B3 + (A3 B3) · A2·B2 + (A3 B3) · (A2 B2) · A1· B1 + (A3 B3) · (A2 B2) · (A1 B1) · A0·B0 10 of 12 5
8-bit Magnitude Comparator 74x682 – Does not have cascading inputs (unlike 74x85) – Does not provide a “less than” output Compares equality using 4 XNOR gates PEQQ_L 74x682 2 P0 3 Q0 4 P1 5 Q1 6 P2 7 Q2 19 PEQ Q 8 P3 9 Q3 PGTQ_L Compares if 11 P4 P[7–0] > Q[7–0] 12 Q4 1 13 PGT Q P5 14 Q5 15 P6 16 Q6 17 P7 18 Q7 11 of 12 Arithmetic Conditions from 74x682 Not-provided conditions PNEQ can be implemented as a 74x04 function of outputs 1 2 PEQQ PEQQ_L and PGTQ_L U2 74x04 4 PGTQ U2 74x682 74x00 1 3 PGEQ 2 19 U3 PEQQ PLEQ 1 PGTQ 74x08 1 3 PLTQ 2 U1 U4 12 of 12 6
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