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14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #11: Encoders Encoders versus Decoders An encoder performs the inverse function as a decoder The simplest encoder

  1. 14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #11: Encoders Encoders versus Decoders  An encoder performs the inverse function as a decoder  The simplest encoder to build is a 2 n -to- n ( binary encoder ) Decoder Encoder 2 of 18 1

  2. Example: A decimal-to-BCD encoder  A decimal-to-BCD encoder – Inputs: 10 bits corresponding to decimal digits 0 through 9, (D 0 , …, D 9 ) – Outputs: 4 bits with BCD codes – Function: If input bit D i is a “1”, then the output (A 3 , A 2 , A 1 , A 0 ) is the BCD code for i Encoder D9 D8 I9 D7 I8 A3 I7 A2 I6 A1 D0 A0 I0 Example: “7”, “3”, “8” “0111”, “0011”, “1000” 3 of 18 Truth table of the decimal-to-BCD encoder  From the truth table, encoder outputs: A3 = D8 + D9 A2 = D4 + D5 + D6 + D7 A1 = D2 + D3 + D6 + D7 A0 = D1 + D3 + D5 + D7 + D9  We made use of the fact that only one input can be “1” at one time  Note that if none button is pushed, output is also “0000”  What if two buttons are pushed simultaneously? —E.g. D1 and D2 together: A0=A1=1 and A2=A3=0 (0011) which is the same as if D3 were pushed! Inputs Outputs D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 4 of 18 2

  3. Binary Encoders ■ General structure: ■ 8-to-3 encoder: Binary Y0 encoder I0 I0 Y0 I1 I1 Y1 Y1 I2 n outputs I2 2 n inputs I3 Y n –1 I4 I2 n –1 Y2 I5 I6 I7 Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y3 = I4 + I5 + I6 + I7 5 of 18 Priority Encoders  If more than one input value is “1” , then the encoder just designed does not work properly  An encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder  Among the “1” s that appear, it selects the most significant input position (or the least significant input position) containing a “1” and produces the corresponding binary code for that position  A system with 2 n requestors and a “request encoder” that indicates which request signal is asserted at any time: Request encoder REQ1 REQ2 Requestor’s REQ3 Requests number for service REQN 6 of 18 3

  4. Exercise: Design a 4-input priority encoder with active low inputs  Highest priority is given to most significant input “1” present (I3 … I0)  Code outputs: A1, A0 and IDLE (indicates no input present) Intermediate variables: Encoder outputs: H3 = I3  A1 = H2 + H3 H2 = I2  ·I3 A0 = H1 + H3 H1 = I1  ·I2·I3 IDLE = I3·I2·I1·I0 H0 = I0  ·I1·I2·I3 Truth table: Priority encoder Inputs Outputs I3 I3 I2 I1 I0 A1 A0 IDLE A1 I1 ? 1 1 1 1 x x 1 I2 A0 1 1 1 0 0 0 0 1 1 0 x 0 1 0 IDLE I0 1 0 x x 1 0 0 0 x x x 1 1 0 7 of 18 Exercise: Design a 4-input priority encoder with active low inputs  Highest priority is given to most significant input “1” present (I3 … I0)  Code outputs: A1, A0 and IDLE (indicates no input present)  We could use a Karnaugh map to get equations, but can be read directly from the truth table and manually optimized if careful: X·Y  + X  = [ (T2) X + 1 = 1 ] A1 = I3·I2  + I3  = I2  + I3  X·Y  + X  ·(Y  +1) = X·Y  + X  ·Y  + X  = [ (T10) X  Y + X  Y  = X ] A0 = I3·I2·I1  + I3  = I2·I1  + I3  Y  + X  IDLE = I3·I2·I1·I0 Truth table: Priority encoder Inputs Outputs I3 I3 I2 I1 I0 A1 A0 IDLE A1 I1 ? 1 1 1 1 x x 1 I2 A0 1 1 1 0 0 0 0 1 1 0 x 0 1 0 IDLE I0 1 0 x x 1 0 0 0 x x x 1 1 0 8 of 18 4

  5. 8-input Priority Encoder  Logic symbol for a generic 8-input priority encoder Priority encoder I7 I6 A2 I5 A1 I4 A0 I3 I2 IDLE I1 I0 9 of 18 A Generic 8-input Priority Encoder  Truth table Priority encoder Inputs Outputs I7 I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 IDLE I6 A2 0 0 0 0 0 0 0 0 0 0 0 1 I5 A1 I4 x x x x x x x 0 A0 1 1 1 1 I3 0 x x x x x x 0 1 1 1 0 I2 IDLE 0 0 x x x x x 0 1 1 0 1 I1 I0 0 0 0 x x x x 0 1 1 0 0 0 0 0 0 x x x 0 1 0 1 1 0 0 0 0 0 x x 0 1 0 1 0 0 0 0 0 0 0 x 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 10 of 18 5

  6. Priority-Encoder Logic Equations Define intermediate variables, s.t. Hi is “1” Priority encoder if and only if Ii is the highest-priority input: I7 H7 = I7 I6 A2 H6 = I6 · I7  I5 A1 I4 A0 H5 = I5 · I6  · I7  I3 I2 IDLE ··· I1 H0 = I0 · I1  · I2  · I3  · I4  · I5  · I6  · I7  I0 Encoder outputs : A2 = H4 + H5 + H6 + H7 A1 = H2 + H3 + H6 + H7 A0 = H1 + H3 + H5 + H7 The IDLE output is “1” if no inputs are “1”: IDLE = (I0 + I1 + I2 + I3 + I4 + I5 + I6 + I7)  = I0  · I1  · I2  · I3  · I4  · I5  · I6  · I7  11 of 18 74x148 8-input Priority Encoder  Active-low I/O  EI = Enable Input  GS = Group Select (“Got Something”, as opposed to IDLE=“Got Nothing”) – One or more of the request inputs are asserted and EI is asserted  EO = Enable Output – No request input is asserted and EI is asserted (corresponds to IDLE) Generic 74x148 priority encoder 5 EI 4 I7 I7 3 6 I6 A2 I6 A2 2 7 I5 A1 I5 A1 1 9 I4 I4 A0 A0 13 I3 I3 12 14 I2 I2 GS IDLE 11 15 I1 EO I1 10 I0 I0 12 of 18 6

  7. Truth Table for a 74x148 Encoder 74x148 pass 5 EI 4 I7 3 6 I6 A2 Inputs Outputs 2 7 I5 A1 1 9 I4 A0 13 I3 EI_L I0_L I1_L I2_L I3_L I4_L I5_L I6_L I7_L A2_L A1_L A0_L GS_L EO_L 12 14 I2 GS 11 15 I1 EO 10 1 x x x x x x x x 1 1 1 1 1 I0 0 x x x x x x x 0 1 0 0 0 0 0 x x x x x x 1 0 1 0 0 0 1 0 x x x x x 1 1 0 1 0 0 1 0 0 x x x x 1 1 1 0 1 0 0 1 1 0 x x x 1 1 1 1 0 1 0 1 0 0 0 x x 1 1 1 1 1 0 1 0 1 0 1 0 x 1 1 1 1 1 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 selected 13 of 18 74x148 Logic Circuit  74x148: (10) I0_L – Enable Input ( EI ) must be (15) EO_L asserted for any output to be asserted (11) I1_L (14) GS_L – Group Select ( GS ) is asserted if ≥ 1 inputs are (12) asserted and EI is asserted I2_L – Enable Output ( EO ) is (9) asserted if no input is A0_L (13) asserted and EI is asserted I3_L (1) I4_L (7) (2) A1_L I5_L (3) I6_L (4) I7_L (6) A2_L (5) EI_L 14 of 18 7

  8. Example 74x148 Outputs ■ 74x148 the A0_L output: A0_L = 0 for I7_L, I5_L, I3_L, I1_L A0_L = (EI·I7 + EI·I6_L·I5 + EI·I6_L·I4_L·I3 + + EI·I6_L·I4_L·I2_L·I1)  ■ 74x148 the A1_L output: A1_L = 0 for I7_L, I6_L, I3_L, I2_L A1_L = (EI·I7 + EI·I6 + EI·I5_L·I4_L·I3 + + EI·I5_L·I4_L·I2)  15 of 18 Cascading Priority Encoders 74x148 5 EI 4 REQ31_L I7 G3A2_L 3 6 REQ30_L I6 A2 G3A1_L 2 7 I5 REQ29_L A1 G3A0_L 1 9 I4 A0 REQ28_L 13 ■ 32-input priority encoder REQ27_L I3 G3GS_L 12 14 REQ26_L I2 GS 11 15 I1 EO REQ25_L 10 using four cascaded 74x148s I0 REQ24_L U1 74x148 G3EO_L 5 EI 4 I7 REQ23_L 3 G2A2_L 6 I6 A2 REQ22_L G2A1_L 2 7 REQ21_L I5 A1 74x00 G2A0_L 1 9 REQ20_L I4 A0 1 6 13 I3 RA4 REQ19_L 2 G2GS_L 12 14 REQ18_L I2 GS 11 15 U5 REQ17_L I1 EO 10 REQ16_L I0 74x00 U2 4 6 RA3 5 74x148 G2EO_L 5 U5 EI 4 REQ15_L I7 1 74x00 G1A2_L 3 6 REQ14_L I6 A2 2 G1A1_L 6 2 7 I5 A1 RA2 REQ13_L 4 G1A0_L 1 9 REQ12_L I4 A0 5 13 U6 REQ11_L I3 G1GS_L 12 14 9 REQ10_L I2 GS 74x00 11 15 I1 EO 10 REQ9_L 8 10 RA1 REQ8_L I0 11 U3 13 U6 74x148 G1EO_L 1 74x00 5 EI 2 6 4 I7 RA0 REQ7_L 4 G0A2_L 3 6 REQ6_L I6 A2 5 G0A1_L 2 7 U7 REQ5_L I5 A1 G0A0_L 1 9 9 REQ4_L I4 A0 74x00 13 I3 10 REQ3_L G0GS_L 8 12 14 RGS REQ2_L I2 GS 12 11 15 REQ1_L I1 EO 13 10 U7 REQ0_L I0 U4 16 of 18 8

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