Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies Zhangcai Huang ∗ †, Hong Yu ∗ , Atsushi Kurokawa† and Yasuaki Inoue ∗ ∗ Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japan †Sanyo Semiconductor Co., Ltd, Gunma, 370-0596 Japan Email: †hzc_2002@asagi.waseda.jp 1
Outline Outline � Background Background � � Analytical expressions for overshooting effect Analytical expressions for overshooting effect � � Considering process variation Considering process variation � � Simulation results Simulation results � � Conclusions Conclusions � 2
Outline Outline � Background Background � � Analytical expressions for overshooting effect Analytical expressions for overshooting effect � � Considering process variation Considering process variation � � Simulation results Simulation results � � Conclusions Conclusions � 3
The differential equation for the CMOS inverter PMOS Ip I CM I CL The input voltage for the falling input ramp is expressed as Vin Vout CM In NMOS “C M is known as the Miller effect, but is seldom of importance in digital circuits. It is, however, of major importance in analog circuits.” Principles of CMOS VLSI Design: A Systems Perspective
I. Background I. Background 1 = 50 − t t t D in 2 1 = + − t t t t D ov r in 2 For traditional process technologies, the effect of overshooting is very small and can be neglected 5
I. Background I. Background The influence of overshooting time on timing analysis The influence of overshooting time on timing analysis t r and td decrease much faster than t ov with the increasing of gate sizes. And t ov is equal to or larger than t r . With the scaling of technology process, t ov becomes much important for delay time. 6
I. Background I. Background The influence of overshooting time on power analysis The influence of overshooting time on power analysis Short-circuit power consumption The overshooting time is one important parameter for power consumption estimation. 7
I. Background I. Background Conventional models for overshooting time Conventional models for overshooting time The overshooting time t ov =0. is neglected The overshooting time is assumed as simple t ov = ( V t / V dd ) t in value J. L. Rossell, …“Charge-based empirical analytical model for the evaluation of expressions power consumption …”, TCAD 2002. 8
Outline Outline � Background Background � � Analytical expressions for overshooting effect Analytical expressions for overshooting effect � � Considering process variation Considering process variation � � Simulation results Simulation results � � Conclusions Conclusions � 9
300 250 PMOS 200 Ip Charging period 150 I CM I CL Current (uA) 100 I L (t ov ) Discharging period 50 Q 2 CM 0 t vmin t ov Q 1 In −50 NMOS −100 0 20 40 60 80 100 120 Times (ps)
II. Proposed Model II. Proposed Model PMOS Ip I CL I CM I CM Vin Vout In C L I n I CL NMOS d V in ( ) ⎡ ⎤ β − ˆ C V V n G S T H N − M ( ) ⎢ ⎥ d t + = − C C V t 1 e ( ) L M ⎢ ⎥ out β − ˆ V V ⎣ ⎦ n G S T H N
II. Proposed Model II. Proposed Model 300 700 600 250 500 200 Charging period 400 150 I p Current (uA) Current (uA) 300 100 I L (t ov ) 200 Discharging period I n 50 Q 2 100 0 t p t ov t vmin t ov Q 1 0 t vmin −50 −100 −100 0 20 40 60 80 100 120 0 20 40 60 80 100 120 Times (ps) Times (ps) 12
II. Proposed Model II. Proposed Model Minimum overshooting time Minimum overshooting time The overshooting time has minimum values. 1 = + − Minimum delay > Minimum overshooting time t t t t D ov r in 2 13
Outline Outline � Background Background � � Analytical expressions for overshooting effect Analytical expressions for overshooting effect � � Considering process variation Considering process variation � � Simulation results Simulation results � � Conclusions Conclusions � 14
III. Considering Process Variation III. Considering Process Variation In recent technologies, the variability of circuit performance due to the process variation has become a significant concern. As process geometries continue to shrink, the evaluation for critical device parameters is becoming more and more difficult due to the significant variations The sensitivities of the overshooting time with respect to the variation sources. With respect to the variation of length. With respect to the variation of threshold voltage. 15
III. Considering Process Variation III. Considering Process Variation 1 = + − t t t t D ov r in 2 Variation of L has no influence on the overshooting time. Variation of L has the influence only on the rising time. Variation of L has significant influence on the gate delay. D. Sinha, …“Gate Sizing Using Incremental Parameterized Statistical Timing Analysis” ICCAD-2005 16
III. Considering Process Variation III. Considering Process Variation 1. With input time decreases, the influence due to the Tox decreases greatly. 2. The influence due to L is 0. 3. With the scaling of process technologies, the variation of Vt increases, the influence due to Vt will increase greatly. International Technology Roadmap for Semiconductors (ITRS) 2005. 17
Outline Outline � Background Background � � Analytical expressions for overshooting effect Analytical expressions for overshooting effect � � Considering process variation Considering process variation � � Simulation results Simulation results � � Conclusions Conclusions � 18
IV. Simulation Results IV. Simulation Results J.L. Rossell: “Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers”, TCAD 2002. 19
IV. Simulation Results IV. Simulation Results J.L. Rossell: “Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers”, TCAD 2002. 20
Outline Outline � Background Background � � Analytical expressions for overshooting effect Analytical expressions for overshooting effect � � Considering process variation Considering process variation � � Simulation results Simulation results � � Conclusions Conclusions � 21
V. Conclusions V. Conclusions � The input The input- -to to- -output coupling capacitance has been proved to output coupling capacitance has been proved to � has significant influence on CMOS gates: timing analysis timing analysis and and has significant influence on CMOS gates: power analysis. . power analysis � The overshooting time has become one of main parts of gate The overshooting time has become one of main parts of gate � delay. delay. � The analytical model for overshooting time is derived. The analytical model for overshooting time is derived. � 1. The overshooting time has minimum value 1. The overshooting time has minimum value 2. Gate delay cannot be smaller than this minimum value. 2. Gate delay cannot be smaller than this minimum value. � Considering process variation: Considering process variation: � 1. The variation due to L has the influence only on output rising time, but 1. The variation due to L has the influence only on output rising time, but has almost no influence on overshooting time. has almost no influence on overshooting time. 2. The variation due to Vt Vt has the most significant influence on has the most significant influence on 2. The variation due to overshooting time with the scaling of technologies. overshooting time with the scaling of technologies. 22
Thank you for your attentions 23
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