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Lecture 10: Sequential Networks: Implementation (Review) CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1


  1. Lecture 10: Sequential Networks: Implementation (Review) CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

  2. Universal*Gates*(review)* • Is*the*following*func7on*a*universal*set* ****f(x,y)*=*xy*+x’y’* ****A.*Yes* ****B.*No* * * 2

  3. Universal*Gates*(review)* • Is*the*following*func7on*a*universal*set* ****f(x,y,z)*=*xyz*+x’y’z’* ****A.*Yes* ****B.*No* * * 3

  4. Moore Design Output is a function of present state only

  5. Mealy Design Output is a function of present state and input

  6. Implementation Procedure 1. Draw*State*Diagram* [Mealy*or*Moore*as*required] ** * 2.*Assign*the*state,*input,*output*encoding* * 3.*Draw*State*Transi7on*Table** * 4.*Derive*Boolean*Expressions* * 5.*Draw*circuit** *

  7. Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = baa, the output y(t) = 1, otherwise y(t) = 0. Implement the corresponding circuit using JK flip flops Draw the Moore and Mealy state diagram 7

  8. STEP 1 : Moore State Diagram a a b b a a S0 S1 S2 S3 0 1 0 0 b b x(t) y(t) C1 C2 CLK S(t) Moore Machine

  9. STEP 1 : Mealy State Diagram a/1 a/0 Looking for baa b/0 b/0 a/0 S0 S1 S2 b/0 x(t) y(t) C1 C2 CLK S(t) Mealy Machine

  10. STEP 2 : State, Input and Output Encoding State Encoding a/1 a/0 b/0 S0: S1: b/0 a/0 S0 S1 S2 S2: b/0 Input Encoding a: 0 b: 1 PI Q: How many binary variables are needed to encode the states in the above diagram A. Three B. Two C. One

  11. STEP 3: State Table State Encoding 0/1 0/0 Q 1 Q 0 1/0 S0: 0 0 1/0 0/0 S1: 0 1 00 01 10 1/0 S2: 1 0 X(t) Q 1 (t) Q 0 (t) 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0

  12. STEP 3: State Table State Assignment 0/1 0/0 Q 1 Q 0 1/0 S0: 0 0 1/0 0/0 S1: 0 1 00 01 10 1/0 S2: 1 0 id x(t) Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 1 0 0 3 1 0 1 0 1 0 4 0 1 0 0 0 1 5 1 1 0 0 1 0

  13. Mapping the variables to the Mealy circuit id x(t) Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 0 0 …… …… ……………...... ………………… .………….... …… …... ....................... ………………… ……………. C2 C1

  14. Excitation table using JK flip flop id x(t) Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 0 0 … …... ………… …………………… ………….... … ....... …............. ……………… …………… x(t) Q 0 (t) y(t) JK C2 C1 Q 1 (t) JK

  15. Excitation table using JK flip flop id x(t) Q 1 (t) Q 0 (t) J 0 (t) K 0 (t) J 1 (t) K 1 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 1 0 0 3 1 0 1 0 1 0 4 0 1 0 0 0 1 5 1 1 0 0 1 0 PI Q: Which of the following completely specifies the value of J 0 (t) in the above table? JK Q(t+1) NS A. Q 0 (t) PS 0 1 B. Q 1 (t), Q 0 (t) 0- 1- 0 1 Q(t) -1 -0 C. Q 0 (t), Q 0 (t+1) D. None of the above

  16. Excitation table using JK flip flop id x(t) Q 1 (t) Q 0 (t) J 0 (t) K 0 (t) J 1 (t) K 1 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 X 0 X 0 0 0 1 1 0 0 1 X 0 X 0 1 0 2 0 0 1 X 1 1 X 1 0 0 3 1 0 1 X 0 0 X 0 1 0 4 0 1 0 0 X X 1 0 0 1 5 1 1 0 1 X X 1 0 1 0 JK Q(t+1) NS PS 0 1 0- 1- 0 1 Q(t) -1 -0

  17. STEP 4, 5: Boolean Expressions, Circuit id x(t) Q 1 (t) Q 0 (t) J 0 (t) K 0 (t) J 1 (t) K 1 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 1 0 0 1 0 0 0 … …... ………… …………………… ………….... … ....... …............. ……………… …………… x(t) Q 0 (t) y(t) JK C2 C1 Q 1 (t) JK

  18. STEP 4: Boolean Expressions id x(t) Q 1 (t) Q 0 (t) J 0 (t) K 0 (t) J 1 (t) K 1 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 X 0 X 0 0 0 1 1 0 0 1 X 0 X 0 1 0 2 0 0 1 X 1 1 X 1 0 0 3 1 0 1 X 0 0 X 0 1 0 4 0 1 0 0 X X 1 0 0 1 5 1 1 0 1 X X 1 0 1 0 K-map for J 0 (t): 0 2 6 4 1 3 7 5

  19. STEP 4: Boolean Expressions id x(t) Q 1 (t) Q 0 (t) J 0 (t) K 0 (t) J 1 (t) K 1 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 X 0 X 0 0 0 1 1 0 0 1 X 0 X 0 1 0 2 0 0 1 X 1 1 X 1 0 0 3 1 0 1 X 0 0 X 0 1 0 4 0 1 0 0 X X 1 0 0 1 5 1 1 0 1 X X 1 0 1 0 Q 1 (t) Q 0 (t) K-map for J 0 (t): x(t) 0 2 6 4 0 X X 0 J 0 (t)= x(t) 1 3 7 5 1 X X 1

  20. STEP 4: Boolean Expressions id x(t) Q 1 (t) Q 0 (t) J 0 (t) K 0 (t) J 1 (t) K 1 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 X 0 X 0 0 0 1 1 0 0 1 X 0 X 0 1 0 2 0 0 1 X 1 1 X 1 0 0 3 1 0 1 X 0 0 X 0 1 0 4 0 1 0 0 X X 1 0 0 1 5 1 1 0 1 X X 1 0 1 0 J 0 (t)= x(t) K 0 (t)= x(t)’ J 1 (t)= x(t)’Q 0 (t) K 1 (t)= 1

  21. STEP 5: Next state Logic id x(t) Q 1 (t) Q 0 (t) J 0 (t) K 0 (t) J 1 (t) K 1 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 0 0 … …... ………… …………………… ………….... … ....... …............. ……………… …………… x(t) Q 0 (t) y(t) JK C2 J 0 (t)= x(t) K 0 (t)= x(t)’ Q 1 (t) J 1 (t)= x(t)’Q 0 (t) JK K 1 (t)= 1

  22. STEP 5: Output logic id x(t) Q 1 (t) Q 0 (t) J 0 (t) K 0 (t) J 1 (t) K 1 (t) Q 1 (t+1) Q 0 (t+1) y(t) 0 0 0 0 0 0 0 … …... ………… …………………… ………….... … ....... …............. ……………… …………… x(t) Q 0 (t) J 0 (t)= x(t) y(t) K 0 (t)= x(t)’ JK J 1 (t)= x(t)’Q 0 (t) K 1 (t)= 1 Q 1 (t) JK y(t)= x(t)’Q 1 (t)

  23. Modified 2 bit counter x(t) Q D Q’ Q 0 (t) Q Q 0 (t) D Q’ Q 1 (t) y(t) Q 1 (t) CLK Q: Is the above circuit a Moore or a Mealy? A. Moore B. Mealy 23

  24. Free running 2-bit counter using T-flip flops S 0 * S 3 * S 1 * S 2 * Excitation table id Q 1 (t) Q 0 (t) T 1 (t) T 0 (t) Q 1 (t+1) Q 0 (t+1) 0 0 0 0 1 0 1 1 0 1 1 1 1 0 2 1 0 0 1 1 1 3 1 1 1 1 0 0 24

  25. Free running counter with T flip flops Q 0 T 0 (t) = 1 1 Q T T 1 (t) = Q 0 (t) Q’ Q Q 1 T Q’ T 1 Q: Notice Q 1 is not fed back into the circuit. Does this mean we have only one state variable? A. Yes B. No 25

  26. Problem 2-II of exercise 4 Q: A state machine is described by the following equations: Q 1 ( t + 1) = Q 0 ( t ) + Q ′ 1 ( t ) x ( t ), Q 0 ( t + 1) = Q 1 ( t ) � x ( t ) + Q 0 ( t ) x ( t ), y ( t ) = Q ′ 1 ( t ) Q 0 ( t ) + x ( t ) a) Write the state table b) Design the system with two T-flip flops and a minimal AND-OR-NOT network c) Design the system with two SR-flip flops and a minimal AND-OR-NOT network 26

  27. Q 1 ( t + 1) = Q 0 ( t ) + Q ′ 1 ( t ) x ( t ), Q 0 ( t + 1) = Q 1 ( t ) � x ( t ) + Q 0 ( t ) x ( t ), y ( t ) = Q ′ 1 ( t ) Q 0 ( t ) + x ( t ) id x(t) Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 27

  28. What is the next step to arrive at the circuit implementation? A. Draw the state diagram of the problem B. Obtain the excitation table C. Get the reduced expression for the next state as a function of present state and inputs id x(t) Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) 0**************0** 0 0 0 0 1**************0* 1 0 0 1 0**************1* 2 0 1 0 1**************1* 3 0 1 1 1**************1* 4 1 0 0 1**************1* 5 1 0 1 6 1 1 0 0 0 7 1 1 1 1 1 28

  29. SR Q(t+1) NS PS 0 1 0 0- 10 1 01 -0 Q(t) id x(t) Q 1 (t) Q 0 (t) S 0 (t) R 0 (t) S 1 (t)R 1 (t) Q 1 (t+1) Q 0 (t+1) 0**************0** 0 0 0 0 1**************0* 1 0 0 1 0**************1* 2 0 1 0 1**************1* 3 0 1 1 1**************1* 4 1 0 0 1**************1* 5 1 0 1 6 1 1 0 0 0 7 1 1 1 1 1 29

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