Digital Design Discussion: Logic Gates Subtractor with Simple and - PowerPoint PPT Presentation

Principles Of Digital Design Discussion: Logic Gates Subtractor with Simple and Complex Gates Low Fuel Detector with Simple and Complex Gates

Full Subtractor Design with Simple Gates(1)  Step 1. Create truth table for full subtractor which has three 1-bit inputs x, y and borrow z , and two 1- bit outputs difference d and borrow b determined by:  d = x-y-z  b = 1 if x<(y+z), else 0 x y z b d 0 0 0 0 0 0 0 1 1 1 A 1 1 1 1 0 0 1 0 1 1 0 1 1 1 0 B 1 1 1 0 0 0 1 Borrows 0 0 1 1 1 0 1 0 0 Difference 1 1 0 1 0 1 1 0 0 0 1 1 1 1 1 Subtractor Diagram Binary Subtraction Example 1-bit Subtractor Truth Table Logic Gates 2 DIGITAL DESIGN 101, University of California

Full Subtractor Design with Simple Gates(2)  Step 2. Implement subtractor with simple gates library (Inverter, And, OR, NAND, NOR, XOR, XNOR) .  2-1. Generate Boolean equation using K-map xy xy 00 01 11 10 z 00 01 11 10 z 0 1 3 2 0 1 3 2 1 1 1 0 b = x’(y ⊕ z )+yz d = x’(y ⊕ z )+x(y  z ) 4 5 7 6 4 5 7 6 = x ⊕ y ⊕ z 1 1 1 1 1 1 1  2-2. Draw schematic z y  2-3. Calculate delay z to b = 4.8 2.4 4.2 x, y to d = 8.4 b x 2.4 2.4 4.2 d Logic Gates 3 DIGITAL DESIGN 101, University of California

Full Subtractor Design with Complex Gates(1)  Step 1. Create truth table for full subtractor which has three 1-bit inputs x, y and borrow z , and two 1- bit outputs difference d and borrow b determined by:  d = x-y-z  b = 1 if x<(y+z), else 0 x y z b d 0 0 0 0 0 0 0 1 1 1 A 1 1 1 1 0 0 1 0 1 1 0 1 1 1 0 B 1 1 1 0 0 0 1 Borrows 0 0 1 1 1 0 1 0 0 Difference 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 Subtractor Diagram Binary Subtraction Example 1-bit Subtractor Truth Table Logic Gates 4 DIGITAL DESIGN 101, University of California

Full Subtractor Design with Complex Gates(2)  Step 2. Implement subtractor with complex gates library  2-1. Generate Boolean Graphic Functional Delay Name in ns Symbol Expression equation from K-map 2– wide, F F = ( wx + yz ) ′ 2– input 2.0 xy AOI 00 01 11 10 z 0 1 3 2 3– wide, 1 0 F F = ( uv + wx + yz ) ′ 2– input 2.4 4 5 7 6 AOI 1 1 1 1 2– wide, F = ( uvw + xyz ) ′ 3– input 2.2 F b = x’z + x’y + yz AOI xy 2– wide, 00 01 11 10 z F F = (( w + x )( y + z )) ′ 2– input 2.0 0 1 3 2 1 1 0 OAI 3– wide, 4 5 7 6 F = (( u + v )( w + 1 1 1 2– input 2.2 F x )( y + z )) ′ OAI d = x’y’z + x’yz’ + xy’z’ + xyz 2– wide, F = (( u + v + w )( x + 3– input 2.4 y + z )) ′ F OAI Logic Gates 5 DIGITAL DESIGN 101, University of California

Full Subtractor Design with Complex Gates(3)  2-2. Transform Boolean equation to match the gate library  b = (x’z + x’y + yz )’’ //De Morgan’s Law = ( (x’z)’ (x’y)’ (yz)’ )’ // De Morgan’s Law = ((x+z’) (x+y’) (y’+z’))’ // 3 wide OAI (2.2)  d = (x’y’z + x’yz’ + xy’z’ + xyz)’’ //De Morgan’s Law = ((x’y’z + x’yz’)’ (xy’z’+xyz)’)’ // 2 wide AOI (2.2),and NAND(1.4)  2-3. Draw schematic  2-4. Calculate delay z to b = 3.2 x,y to d = 4.6 Logic Gates 6 DIGITAL DESIGN 101, University of California

Low Fuel Detector using Simple Gates A car has a fuel-level detector that outputs the current fuel-level as a 3-bit binary number, with 000 meaning empty and 111 meaning full. Create a circuit that illuminates a “low fuel” indicator light (by setting an output L to 1) when the fuel level drops below level 3. Step 1. Derive a Boolean equation a b c L K-Map for Z 0 0 0 1 b c 0 0 1 1 a 00 01 11 10 0 1 0 1 0 0 1 1 1 0 1 1 0 L = a’b’ + a’c’ 1 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0 Truth Table for Z 7 Logic Gates DIGITAL DESIGN 101, University of California

Low Fuel Detector using Simple Gates Step 2. Draw schematic using simple gates L = a’b’ + a’c’ a 1 2.4 L 2.4 b 1 2.4 c 1 Step 3. Determine delay delay = 1 + 2.4 + 2.4 = 5.8 Logic Gates DIGITAL DESIGN 101, University of California

Low Fuel Detector using Complex Gates A car has a fuel-level detector that outputs the current fuel-level as a 3-bit binary number, with 000 meaning empty and 111 meaning full. Create a circuit that illuminates a “low fuel” indicator light (by setting an output L to 1) when the fuel level drops below level 3. Step 1. Derive a Boolean equation a b c L K-Map for Z 0 0 0 1 b c 0 0 1 1 a 00 01 11 10 0 1 0 1 0 0 1 1 1 0 1 1 0 L = a’b’ + a’c’ 1 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0 Truth Table for Z 9 Logic Gates DIGITAL DESIGN 101, University of California

Low Fuel Detector using Complex Gates Step 2. Select proper gates from complex gates library 2-wide, 2-input AOI and inverters can be used for equation L = a’b’ + a’c’ Step 3. Draw schematic using complex gates a 1 L 1 1 1 b 1 2.0 c 1 Step 4. Determine delay delay = 1 + 2 + 1 = 4 Logic Gates DIGITAL DESIGN 101, University of California