Fast Dynamic Simulation of VLSI circuits using Reduced Order Compact Macromodel of Standard Cells Shivam Priyadarshi, Nikhil Kriplani, T. Robert Harris, and Michael B. Steer North Carolina State University 2010 IEEE International Behavioral Modeling and Simulation Conference 24 September 2010 1
Overview Motivation Reduced Order Macromodeling Macromodel Implementation examples CMOS Inverter Macromodel CMOS NAND Macromodel Results and Discussion Conclusion 2
Motivation Some applications require Long Dynamic Simulation Transient Electro-thermal simulation to see the impact of self heating of devices on circuit performance Transistor-level simulation is challenging for such applications Extremely Time consuming High Memory requirement A Dynamic Simulation methodology is required which can Reduce computational and storage cost Produce sufficiently accurate results 3
Motivation Macromodel based simulation methodology An alternative to transistor-level simulation In past, used for timing analysis of standard cell based VLSI circuits ◊ Table look up models [1-3] ◊ Current Source models [4-6] Proposed Dynamic simulation methodology Uses physics based reduced order compact macromodels of standard cells in constructing large scale circuits Suitable for applications where long duration dynamic simulation is required ◊ Electro-thermal simulation to study the impact of transient thermal effects Can be used for fast and accurate timing and power characterization of standard cells 4
Overview Motivation Reduced Order Macromodeling Macromodel Implementation examples CMOS Inverter Macromodel CMOS NAND Macromodel Results and Discussion Conclusion 5
Reduced Order Macromodeling Reduced Order Macromodel of a circuit Preserve the input-output behavior Reduces the complexity of the circuit Can significantly reduce simulation run time and memory requirements Developed reduced order macromodels of standard cells Describe the behavior using fewer number of state variables compared to equivalent transistor-level implementation ◊ Reduction in state variables reduces complexity Based on EKV MOSFET model equations ◊ Physical basis make them accurate Implemented in multi-physics simulator fREEDA 6
fREEDA: A Universal Circuit Simulator • Multi-physics simulator: Concurrent EM, Electrical, Mechanical and Thermal Simulations are possible. • Follow State Space simulation approach • Port voltages and currents are expressed as functions of state variables and their derivatives. m dx d x = v ( ) t u x t ( ), ,..., , x ( ) t NL D m dt dt • Supports high dynamic range Transient, m dx d x = Harmonic balance, DC and AC analysis i ( ) t w x t ( ), ,..., , x ( ) t NL D m dt dt • Enables Rapid model development • Uses Object Oriented Paradigm (C++) : Drastically reduces the amount of code required to implement a model • Uses Automatic Differentiation Packages: Eliminates the need of coding the derivatives 7
Macromodel development flow Identify the state variables from standard cell schematic Reduce the number of internal nodes through parallel and series transistor merging Represent the bulk referenced drain, gate and source voltages of remaining transistors in terms of state variables Formulate the static current entering into each port as functions of state variables Formulate the dynamic current entering into each port as functions of state variables and their derivatives 8
Overview Motivation Reduced Order Macromodeling Macromodel Implementation examples CMOS Inverter Macromodel CMOS NAND Macromodel Results and Discussion Conclusion 9
CMOS Inverter Macromodel • Uses 3 state variables VDD • Transistor level implementation requires 6 I VDD state variables I P = = = x [0] VDD x , [1] V , and x [2] V in out IN OUT I out I in I N • Represent bulk referenced drain and gate voltages in terms of state variables = = − GND V x [2], V x [2] x [0] db_N db_P = = − V x [1], V x [1] x [0] gb_N gb_P 10
CMOS Inverter Macromodel • Formulate the total current entering into each port • Dynamic current is calculated by taking the time derivative of charge dQ dQ dQ dQ dQ gN gP = + = + + + = − + dN dP VDD I I I I I ( I ) in out N P VDD P dt dt dt dt dt • Based on EKV MOSFET model equations, static currents and charges are formulated as functions of bulk referenced drain and gate voltages of NMOS and PMOS { } ( ) = I , I , Q , Q , Q , Q , Q f V , V , V , V N P gN gP dN dP VDD db_N db_P gb_N gb_P 11
CMOS Inverter Macromodel 1.5 1.6 Macromodel 1.4 Transistor-level 1.2 Input voltage Macromodel output 1 1 Input Voltage (V) Transistor-level output Voltage (V) 0.8 0.6 0.5 0.4 0.2 0 0 -0.2 0 0.5 1 1.5 2.95 2.96 2.97 2.98 2.99 3 Time (s) Output Voltage (V) -5 x 10 Comparison of DC transfer characteristic and transient characteristic of the Inverter macromodel with transistor-level implementation on 150 nm CMOS process 12
CMOS NAND Macromodel VDD I VDD • Uses 4 state variables • Transistor level implementation requires 12 P1 P2 state variables I P1 I P2 IN 1 = = = = OUT x [0] VDD x , [1] V , [2] x V , and x [3] V in1 in2 out I IN1 I out N1 IN 2 • Merge series transistors in single transistor I N +i n = N1+N2 I IN2 x N2 • Represent bulk referenced drain, gate and source voltages of PMOS transistors in terms of state variables GND = − = − = V x [3] x [0], V x [1] x [0], and V 0 db_P1 gb_P1 sb_P1 = − = − = V x [3] x [0], V x [2] x [0], and V 0 db_P2 gb_P2 sb_P2 13
CMOS NAND Macromodel • Depending upon the input voltages, it is assumed that one of the NMOS transistors is VDD conducting, i.e. acting as a resistance and I VDD current through the other NMOS transistor is flowing through the series chain P1 P2 I P1 I P2 IN 1 > if ( [1] x [2]) x OUT I IN1 I out = = = V x [3], V x [2] , and V 0 db_N2 gb_N2 sb_N2 N1 IN 2 dQ β = β β β + β = dN2 I N +i n /( ), and i = N1+N2 eq 1 2 1 2 n I IN2 x dt else N2 = = = V x [3], V x [1], and V 0 db_N1 gb_N1 sb_N1 dQ β = β β β + β = dN1 /( ), and i GND eq 1 2 1 2 n dt 14
CMOS NAND Macromodel • Formulate the current entering into each port VDD I VDD dQ dQ = + + + + + dP1 dP2 I I I I i out P1 P2 N n dt dt P1 P2 I P1 I P2 dQ IN 1 = − + + VDD I I I OUT VDD P1 P2 dt I IN1 I out N1 dQ dQ dQ dQ IN 2 = gN1 + gP1 = gN2 + gP2 I , and I I N +i n IN1 IN2 = N1+N2 dt dt dt dt I IN2 x N2 • Finally based on EKV MOSFET model equations, static currents and charges are formulated as functions of the state variables GND { } ( ) = − I , I , Q , Q , Q , Q , Q f x [0 3] P1-P2 N VDD dP1-P2 dN1-N2 gP1-P2 gN1-N2 15
CMOS NAND Macromodel • Macromodel is completely parameterized in terms of process and geometry parameters such as oxide thickness, junction depth, effective channel length, width, and channel doping. • All the temperature dependent device parameters are formulated as function of temperature • Can easily be transformed to an electro-thermal model by introducing temperature as an additional state variable • Small geometry effects such as channel length modulation, source drain charge sharing, velocity saturation are modeled based on EKV MOSFET formulation 16
CMOS NAND Macromodel 1.4 1.2 Output Voltage (V) 1 0.8 Macromodel 0.6 Transistor-level 0.4 0.2 0 -0.2 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 Time (s) -5 x 10 Comparison of DC transfer characteristic and transient characteristic of the NAND macromodel with transistor-level implementation on 150 nm CMOS process 17
Overview Motivation Reduced Order Macromodeling Macromodel Implementation examples CMOS Inverter Macromodel CMOS NAND Macromodel Results and Discussion Conclusion 18
Results and Discussion Reduced order macromodels of more complex cells such as XOR, Latch, Adder and D-Flip-Flop are built. Macromodels are based on device equations Produce results which are in excellent agreement with transistor- level simulation 1.5 Standard Cells Delay error (%) Inverter 0.01 1 2-Input NAND 0.11 Macromodel Transistor-level Bit[7] (V) SR Latch 0.18 D-Flip-Flop 0.33 0.5 8-bit Shift Register 0.80 0 2 3 4 5 6 Time (s) -5 Transient simulation result of 8-bit x 10 shift register 19
Results and Discussion The simulation time and memory usage of the macromodel and equivalent transistor-level implementations are compared by running the transient simulation in fREEDA State variable based fixed time step time marching transient analysis method is used The simulations are performed on a 3 GHz Intel Xeon server with 32 GB of RAM Both kinds of circuits, combinational and sequential, are considered for comparison. 20
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