Hardware/Software Hardware/Software Codesign Environments Codesign - PDF document

12/12/01 Hardware/Software Hardware/Software Codesign Environments Codesign Environments Gert Jervan Gert Jervan IDA/SaS SaS/ESLAB /ESLAB IDA/ Overview Overview Embedded system design process � Traditional � Codesign The COSYMA system The POLIS approach SpecSyn Credits: Rolf Ernst, Sushant Jain, Vivek Sinha Gert Jervan, IDA/SaS Gert Jervan, IDA/ SaS/ESLAB /ESLAB -2 - 2- - HW/SW Codesign Environments HW/SW Codesign Environments 1

12/12/01 Design process Design process customer/ requirements definition support marketing (CAD, test, ...) specification system architect system architecture development SW development HW design interface design • application SW • HW architecture design • SW driver dev. • compilers etc. • HW interface • HW synthesis • operating syst. • physical design synthesis SW HW developer designer integration and test reused components Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -3 3- - - HW/SW Codesign Environments HW/SW Codesign Environments Co-synthesis design flow Co-synthesis design flow system function constraints and OS, constraints and user directives component & user directives communication compilation& libraries system analysis intermediate HW/SW partitioning HDL generation code generation & scheduling code generation HL synthesis co-simulation, analysis object code HW model object code HW model Gert Jervan, IDA/SaS Gert Jervan, IDA/ SaS/ESLAB /ESLAB -4 4- - - HW/SW Codesign Environments HW/SW Codesign Environments 2

12/12/01 Co-design using co-synthesis and design space exploration Co-design using co-synthesis and design space exploration hardware software customer system designer developer architect • • specification parameter change specification parameter change • • high level transformations high level transformations constraints and OS, system function constraints and user directives component & user directives communication compilation& libraries system analysis intermediate code HW/SW partitioning& estimations HDL generation generation scheduling code generation HL synthesis cost, co-simulation analysis performance, ... object code HW model object code HW model Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -5 5- - - HW/SW Codesign Environments HW/SW Codesign Environments COSYMA COSYMA COSYMA ( COSY nthesis for e M bedded micro A rchitectures) Achim Österling, Thomas Benner, Rolf Ernst, Dirk Herrmann, Thomas Scholz, Wei Ye Technische Universität Braunschweig Germany Gert Jervan, IDA/SaS Gert Jervan, IDA/ SaS/ESLAB /ESLAB -6 6- - - HW/SW Codesign Environments HW/SW Codesign Environments 3

12/12/01 COSYMA - an Overview COSYMA - an Overview A platform for exploration of the HW/SW co-synthesis techniques Covers almost entire design flow Limited target architecture Is used mainly for design-space exploration where it gives fast response times Gert Jervan, IDA/SaS Gert Jervan, IDA/ SaS/ESLAB /ESLAB -7 7- - - HW/SW Codesign Environments HW/SW Codesign Environments The COSYMA Design Flow The COSYMA Design Flow C Processes Constraints and user directives Compiler Simulation and profiling Communication Models Process scheduling HW/SW Partitioning C-code gener. HDL-code gener. Synthesis & comm. synth. & comm. synth. directives sim SW Synthesis HL synthesis Synopsys DC obj. code run-time analysis VHDL netlist HW/SW Target model Peripheral modules Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -8 8- - - HW/SW Codesign Environments HW/SW Codesign Environments 4

12/12/01 The COSYMA Design Flow The COSYMA Design Flow C Processes Constraints and user directives Compiler Simulation and profiling Communication Models Process scheduling HW/SW Partitioning C-code gener. HDL-code gener. Synthesis & comm. synth. & comm. synth. directives sim SW Synthesis HL synthesis Synopsys DC obj. code run-time analysis VHDL netlist HW/SW Target model Peripheral modules Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -9 9- - - HW/SW Codesign Environments HW/SW Codesign Environments COSYMA Architecture COSYMA Architecture Standard RISC processor core (a SPARC architecture model with 33 MHz clock and floating point coprocessor with COSYMA) A fast RAM for program and data with single clock cycle access time Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -10 10- - - HW/SW Codesign Environments HW/SW Codesign Environments 5

12/12/01 COSYMA Architecture COSYMA Architecture An automatically generated application specific coprocessor Peripheral units must be inserted by the designer Processor and coprocessor communicate via shared memory in mutual exclusion Gert Jervan, IDA/SaS Gert Jervan, IDA/ SaS/ESLAB /ESLAB -11 11- - - HW/SW Codesign Environments HW/SW Codesign Environments The COSYMA Design Flow The COSYMA Design Flow C Processes Constraints and user directives Compiler Simulation and profiling Communication Models Process scheduling HW/SW Partitioning C-code gener. HDL-code gener. Synthesis & comm. synth. & comm. synth. directives sim SW Synthesis HL synthesis Synopsys DC obj. code run-time analysis VHDL netlist HW/SW Target model Peripheral modules Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -12 12- - - HW/SW Codesign Environments HW/SW Codesign Environments 6

12/12/01 System Spec System Spec The input description may consist of several communicating processes with timing requirements, specified in C x (extension of C supporting parallel processes and timing constraints) Internal data structure: Extended Syntax Graph (ESG) Gert Jervan, IDA/SaS Gert Jervan, IDA/ SaS/ESLAB /ESLAB -13 13- - - HW/SW Codesign Environments HW/SW Codesign Environments The COSYMA Design Flow The COSYMA Design Flow C Processes Constraints and user directives Compiler Simulation and profiling Communication Models Process scheduling HW/SW Partitioning C-code gener. HDL-code gener. Synthesis & comm. synth. & comm. synth. directives sim SW Synthesis HL synthesis Synopsys DC obj. code run-time analysis VHDL netlist HW/SW Target model Peripheral modules Gert Jervan, IDA/SaS Gert Jervan, IDA/ SaS/ESLAB /ESLAB -14 14- - - HW/SW Codesign Environments HW/SW Codesign Environments 7

12/12/01 Scheduling Scheduling C X processes are simulated on a RTL model or analyzed symbolically Scheduling is done by using Scalable Performance Scheduling (SPS) � Resulting a single serialized process � Done before partitioning Alternative approach - combination of scheduling and partitioning Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -15 15- - - HW/SW Codesign Environments HW/SW Codesign Environments Scheduling Scheduling Speedup factor - to estimate the acceleration factor of the target architecture compared to the reference processor Information can be retrieved in an early design stage (before partitioning) Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -16 16- - - HW/SW Codesign Environments HW/SW Codesign Environments 8

12/12/01 The COSYMA Design Flow The COSYMA Design Flow C Processes Constraints and user directives Compiler Simulation and profiling Communication Models Process scheduling HW/SW Partitioning C-code gener. HDL-code gener. Synthesis & comm. synth. & comm. synth. directives sim SW Synthesis HL synthesis Synopsys DC obj. code run-time analysis VHDL netlist HW/SW Target model Peripheral modules Gert Jervan, IDA/SaS Gert Jervan, IDA/ SaS/ESLAB /ESLAB -17 17- - - HW/SW Codesign Environments HW/SW Codesign Environments Partitioning Partitioning Inputs: � ESG with profiling information � CDR file � Synthesis directives Basic block level and is automated HW HW SW SW SW SW Timing constraints! Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -18 18- - - HW/SW Codesign Environments HW/SW Codesign Environments 9

12/12/01 Partitioning Partitioning Partitioning goals: Order of importance Order of importance � meet real-time constraints � minimize hardware costs � minimize the CAD system response time - allow user intervention Simulated Annealing is deployed as an optimization algorithm Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -19 19- - - HW/SW Codesign Environments HW/SW Codesign Environments Partitioning Partitioning Communication is implicit Requires communication analysis and communication synthesis DOES NOT require explicit description of the communication from the user Gert Jervan, IDA/ Gert Jervan, IDA/SaS SaS/ESLAB /ESLAB -20 20- - - HW/SW Codesign Environments HW/SW Codesign Environments 10