FPGArt Painting with an FPGA Niklas Rother, Rebecca Cramer, Tim - PowerPoint PPT Presentation

FPGArt Painting with an FPGA Niklas Rother, Rebecca Cramer, Tim Oberschulte 23.03.2017 1 / 10

Contents Task Implementation What we learned... Statistics Demo 2 / 10

Task ◮ Create a painting application on an FPGA ◮ Use a PS/2 Mouse for input and VGA for output ◮ Implement it completely in hardware (no softcore processor) 3 / 10

Module overview PS/2 Communication PS/2 Protocol Drawing Logic SRAM Clear VGA Output SRAM Controller 4 / 10

Graphic pipeline counter ctl v h mem addr overlay palette SRAM show palette cursor show overlay inside LUT R ′ G ′ B ′ INV R G B 5 / 10

Real hardware Working with real hardware discloses real world problems... The pull-up resistor on the board is not fast enough for pulling the PS/2 clock lane up in one cycle at 40 MHz. Clock Output Input 6 / 10

Hazards happen Hazards happen – so better buffer all input signals... FSM fed by an unbuffered input signal, behaving unpredictable (being in two states at the same time). 7 / 10

Statistics (without overlay) Family: Cyclone II Device: EP2C35F672C6 Total logic elements: 1,690 / 33,216 (5 %) Total combinational functions: 1,683 / 33,216 (5 %) Dedicated logic registers: 225 / 33,216 ( < 1 %) Total registers: 225 Total pins: 99 / 475 (21 %) Total memory bits: 0 / 483,840 (0 %) Embedded Multiplier 9-bit elements: 4 / 70 (6 %) Total PLLs: 1 / 4 (25 %) 8 / 10

Statistics (with overlay) Family: Cyclone II Device: EP2C35F672C6 Total logic elements: 4,634 / 33,216 (14 %) Total combinational functions: 4,626 / 33,216 (14 %) Dedicated logic registers: 225 / 33,216 ( < 1 %) Total registers: 225 Total pins: 99 / 475 (21 %) Total memory bits: 0 / 483,840 (0 %) Embedded Multiplier 9-bit elements: 4 / 70 (6 %) Total PLLs: 1 / 4 (25 %) 9 / 10

DEMO 10 / 10