CMOS beyond Si: Nanometer-Scale I I I -V MOSFETs J. A. del Alamo, X. Cai, J. Lin, W. Lu, A. Vardi, and X. Zhao Microsystems Technology Laboratories Massachusetts Institute of Technology IEEE Bipolar/BiCMOS Circuits and Technology Meeting Miami, FL, October 19-21, 2017 Acknowledgements: • Students and collaborators: D. Antoniadis, E. Fitzgerald • Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung, SRC • Labs at MIT: MTL, EBL
Moore’s Law at 50: the end in sight? 2
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Moore’s Law How far can Si support Moore’s Law? ? 4
The problem: Transistor scaling Voltage scaling Performance suffers Supply voltage: Transistor current density: Intel microprocessors Intel microprocessors What can we do about this? 5
Moore’s Law: it’s all about MOSFET scaling 1. New device structures with improved scalability: Planar bulk Nanowire MOSFET MOSFET Thin-body SOI MOSFET FinFET 2. New materials with improved transport characteristics: n-channel: Si Strained Si SiGe InGaAs p-channel: Si Strained Si SiGe Ge InGaSb 6
I I I -V electronics in your pocket! 7
Historical evolution: I nGaAs High-Electron Mobility Transistor Transconductance (g m =dI D /dV GS ): 8
I nGaAs MOSFETs vs. HEMTs Transconductance (g m =dI D /dV GS ): *inversion-mode * 9
I nGaAs MOSFETs vs. HEMTs Transconductance (g m =dI D /dV GS ): g m =3.45 mS/ μ m *inversion-mode Lin, EDL 2016 * What happened here? 10
Atomic Layer Deposition (ALD) of gate oxide ALD eliminates residual native oxides that pin Fermi level “Self cleaning” Huang, APL 2005 Clean, smooth interface without native oxides • First with Al 2 O 3 , then with other high-K dielectrics • First in GaAs, then in other III-Vs 11
Planar Si and I nGaAs MOSFET Benchmark n-MOSFETs in Intel’s nodes at nominal voltage Comparisons always fraught with danger… Transconductance exceeds Si MOSFETs 12
I nGaAs FinFETs FinFETs 13
Bottom-up I nGaAs FinFETs Aspect-Ratio Trapping Fiorenza, ECST 2010 Si Epi-grown fin inside trench Waldron, VLSI Tech 2014 Sun, VLSI Tech 2017 14
I nGaAs FinFETs @ MI T Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Vardi, • Sub-10 nm fin width DRC 2014, • Aspect ratio > 20 EDL 2015, • Vertical sidewalls IEDM 2015 15
I nGaAs FinFETs @ MI T Mo Mo High-K HSQ SiO 2 HSQ L g W/Mo High-K n + -InGaAs InP InGaAs InGaAs δ - Si InAlAs InP Vardi, VLSI Tech 2016 Vardi, EDL 2016 • Si-compatible process • Contact-first, gate-last process • Fin etch mask left in place double-gate MOSFET 16
Most aggressively scaled FinFET W f =7 nm, L g =30 nm, H c =40 nm (AR=5.7), EOT=0.6 nm: 1E-3 1E-4 V DS =500 mV 500 V GS =-0.5 to 0.75 V DS =50 mV 1E-5 ∆ V GS =0.25 V DIBL=90 mV/V I d [A/ µ m] 400 S sat =100 mV/dev 1E-6 I d [ µ A/ µ m] 300 1E-7 200 1E-8 100 1E-9 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 V GS [V] 0.0 0.1 0.2 0.3 0.4 0.5 g m max =900 µ S/ µ m V DS [V] 1000 Current normalized by 2xH c 800 V DS =0.5 V g m [ µ S/ µ m] 600 At V DS =0.5 V: 400 • g m =900 µS/µm R on =320 Ω .µm • 200 • S sat =100 mV/dec 0 -0.4 -0.2 0.0 0.2 0.4 Vardi, EDL 2016 V GS [V] 17
L g and EOT scaling (W f ~ 20 nm) 1600 250 A: Al 2 O 3 , EOT=2.8 nm 1400 V DS =0.5 V B:Al 2 O 3 /HfO 2 , EOT=1 nm 200 1200 W f = 20-22 nm C: HfO 2 , EOT=0.6 nm EOT ↓ 1000 S sat [mV/dec] 150 g m [ µ S/ µ m] 800 600 100 400 50 200 60 mV/dec EOT ↓ 0 0 0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700 L g [nm] L g [nm] Classical scaling with L g and EOT Vardi, EDL 2016 18
Fin-width scaling (EOT= 0.6 nm) 150 1600 Contaminated by 1400 gate leakage 1200 100 1000 S sat,min [mV/dec] g m max [ µ S/ µ m] 800 W f =22 nm 600 ∆ W f = 5 nm 50 W f =7 nm 60 mV/dec 400 W f =12 nm 200 W f =17 nm 0 7 W f =22 nm 0 0 100 200 300 400 500 600 100 1000 L g [nm] L g [nm] • Non-ideal fin width scaling • Sources: High D it (~5x10 12 cm -2 .eV -1 )? • • mobility degradation? • line edge roughness? Vardi, EDL 2016 19
I nGaAs FinFET benchmarking 20 g m normalized 5.3 Intel by fin width Si FinFETs (V DD =0.8 V) 15 4.3 g m /W f [mS/ µ m] W f Our work (V DS =0.5 V) 10 5.7 1.8 3.3 1.8 InGaAs FinFETs 5 2.2 2.3 1 0.18 0.66 channel 0.23 0.45 0.32 aspect ratio 0.57 0.63 1 0.6 0.8 0 0 20 40 60 Target W f [nm] See latest • First InGaAs FinFETs with W f <10 nm at IEDM • Doubled g m over earlier InGaAs FinFETs 2017! • Short of Si FinFETs sidewall quality? 20
I nGaAs Vertical Nanowire MOSFETs VNW MOSFET 21
Vertical nanowire MOSFET: ultimate scalable transistor L c L spacer L g Vertical NW MOSFET: uncouples footprint scaling from L g , L spacer , and L c scaling 22
I nGaAs Vertical Nanowires @ MI T Key enabling technologies: • RIE = BCl 3 /SiCl 4 /Ar chemistry • Digital Etch (DE) = self-limiting O 2 plasma oxidation + H 2 SO 4 or HCl oxide removal RIE + 5 cycles DE • Radial etch rate=1 nm/cycle • Sub-20 nm NW diameter • Aspect ratio > 10 • Smooth sidewalls Zhao, IEDM 2013 Zhao, EDL 2014 Zhao, IEDM 2014 23
I nGaAs VNW-MOSFETs by top-down approach @ MI T Starting heterostructure: n + InGaAs, 70 nm i InGaAs, 80 nm n + InGaAs, 300 nm n + : 6 × 10 19 cm -3 Si doping Top-down approach: flexible and manufacturable 24
VNW-MOSFET I -V characteristics: D= 40 nm V gs =-0.2 V to 0.7 V in 0.1 V step 300 g m,pk =720 μ S/ μ m 800 250 700 V d = 0.5 V 200 600 I s (µ A/ µ m) g m ( µ S/ µ m ) 500 150 400 100 300 200 50 Zhao, CSW 2017 100 0 0 0.0 0.1 0.2 0.3 0.4 0.5 -0.2 0.0 0.2 0.4 0.6 V ds (V) V gs (V) -3 10 V ds =0.5 V -4 10 Single nanowire MOSFET: -5 10 V ds =0.05 V • L ch = 80 nm I s ( A/ µ m ) -6 10 • 3 nm Al 2 O 3 (EOT = 1.5 nm) -7 10 S lin = 70 mV/dec -8 10 S sat = 80 mV/dec -9 DIBL = 88 mV/V 10 -10 10 -0.2 0.0 0.2 0.4 0.6 V gs (V) 25
Benchmark with Si/ Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs 1400 Si/Ge 1200 InGaAs g m,pk ( µ S/ µ m) 1000 800 1.2 V 600 Our work (V DS =0.5 V) 400 1.2 V 1 200 1 V 1 V 1V 0 0 20 40 60 80 100 Target Diameter (nm) • InGaAs competitive with Si • Need to demonstrate VNW MOSFETs with D<10 nm 26
I nGaAs VNW Mechanical Stability for D< 10 nm 8 nm InGaAs VNWs after 7 DE cycles: Yield = 0% Broken NW Difficult to reach 10 nm VNW diameter due to breakage 27
I nGaAs VNW Mechanical Stability for D< 10 nm Difficult to reach 10 nm VNW diameter due to breakage Yield = 0% Water-based acid is problem: Broken NW Surface tension (mN/m): • Water: 72 • Methanol: 22 • IPA: 23 Solution: alcohol-based digital etch 28
Alcohol-Based Digital Etch Lu, EDL 2017 8 nm InGaAs VNWs after 7 DE cycles: 10% HCl in IPA 10% HCl in DI water Yield = 97% Yield = 0% Broken NW Radial etch rate: 1.0 nm/cycle Radial etch rate: 1.0 nm/cycle Alcohol-based DE enables D < 10 nm 29
D= 5.5 nm VNW arrays 10% H 2 SO 4 in methanol 90% yield • H 2 SO 4 :methanol yields 90% at D=5.5 nm! • Viscosity matters: methanol (0.54 cP) vs. IPA (2.0 cP) 30
I nGaAs Digital Etch First demonstration of D=5 nm diameter InGaAs VNW (Aspect Ratio > 40) 31
Latest! D= 15 nm I nGaAs VNW MOSFET 200 V gs = 0 V to 0.6 V in 0.1 V step R on = 5500 Ω ⋅ µ m Mo contact 150 D = 15 nm I d (µ A/ µ m) o C N 2 RTA 300 100 50 0 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) Single nanowire MOSFET: • L ch = 80 nm • 2.5 nm Al 2 O 3 (EOT = 1.3 nm) Zhao, IEDM 2017 32
Benchmark with Si/ Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs Our latest work (V DS =0.5 V) Even better results at IEDM 2017! Target Most aggressively scaled VNW MOSFET ever 33
I nGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Vapor-Solid-Liquid Selective-Area Epitaxy (SAE) (VLS) Technique Riel, MRS Bull 2014 VNW MOSFETs: path for III-V integration on Si for future CMOS Riel, IEDM 2012 34
Vertical nanowire MOSFET for 5 nm node 5 nm node Yakimets, TED 2015 Bao, ESSDERC 2014 30% area reduction in 6T-SRAM 19% area reduction in 32 bit multiplier Vertical NW: power, performance and area gains w.r.t. Lateral NW or FinFET 35
Conclusions 1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Device performance still lacking for 3D architecture designs 3. III-V Vertical-Nanowire MOSFETs: most likely architecture for future integration with Si 4. Many, MANY issues to work out: sub-10 nm fin/nanowire fabrication , self-aligned contacts , device asymmetry , introduction of mechanical stress , V T control , sidewall roughness , device variability, BTBT and parasitic HBT gain , oxide trapping , self-heating , reliability , NW survivability , co-integration on n- and p-channel devices on Si , interface states, metal routing, contact resistance < 10 -9 Ω .cm -2 , off-state leakage, TDDB, etc.… 36
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