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T42 Transputer Design in FPGA Transputer Design in FPGA T42 Year- -Three Design Status Report Three Design Status Report Year a and Martin ZABEL b , Uwe MIELKE a and Martin ZABEL b , Uwe MIELKE in collaboration w/ Michael BRUESTLE c

  1. T42 – – Transputer Design in FPGA Transputer Design in FPGA T42 Year- -Three Design Status Report Three Design Status Report Year a and Martin ZABEL b , Uwe MIELKE a and Martin ZABEL b , Uwe MIELKE in collaboration w/ Michael BRUESTLE c c in collaboration w/ Michael BRUESTLE a E a E lectronics Engineer, Dresden, Germany, lectronics Engineer, Dresden, Germany, uwe.mielke@t uwe.mielke@t- -online.de online.de b I I nstitute of Computer Engineering, nstitute of Computer Engineering, Technische Universit Technische Universitä ät Dresden t Dresden, Germany, , Germany, martin.zabel@tu martin.zabel@tu- -dresden.de dresden.de b c Electronics Engineer, Vienna, Austria, Electronics Engineer, Vienna, Austria, michael_bruestle@yahoo.com michael_bruestle@yahoo.com c Communicating Process Architectures 2017

  2. T42 in FPGA @ CPA 2016 T42 in FPGA @ CPA 2016 Abstract : : Abstract Our IMS- -T425 binary compatible Transputer design T425 binary compatible Transputer design Our IMS has so far taken over 300 design days. Up to last year has so far taken over 300 design days. Up to last year minimal effort was spend for verification. Now a minimal effort was spend for verification. Now a regression test bench has been brought in place, which regression test bench has been brought in place, which is targeted to verify the design conformance after any is targeted to verify the design conformance after any changes. This T42 Transputer Verification Suite is changes. This T42 Transputer Verification Suite is based on a TVS- -1 work from 1 work from Michael Bruestle Michael Bruestle and and based on a TVS compares the register output of 54 selected instructions compares the register output of 54 selected instructions versus a a true T425 golden reference for up to versus a a true T425 golden reference for up to thousands of data samples. It helped already in T42 thousands of data samples. It helped already in T42 micro- -code debugging and hardware refinement. code debugging and hardware refinement. micro CPA 2017

  3. Agenda Agenda (1) Review (2) Regression Test Bench (3) Transputer Verification Suite (4) TVS-1 Coverage (5) Design Environment (6) Achievements (2017) (7) Outlook (Links ; Verification) (8) Summary & Discussion CPA 2017

  4. T42 in FPGA @ CPA 2014- -16 16 T42 in FPGA @ CPA 2014 (Review) (Review) � 2-stage-pipeline for T42 working in 2014 pre-fetch … is an autonomous FSM *) 1. IF/ID instruction fetch & decode 2. EX execute (using a single or multiple clocks per instruction) memory read/write is part of execute *) � micro code assembler & pre-fetch unit working in 2015 � system control & memory interface working in 2016 � >100 of 134 instructions (~600 lines of µCode) written A lot of HW � How to prove everything is correct ? *) not a pipeline stage CPA 2017

  5. Regression Test Bench ! Regression Test Bench ! � Our T42 Our T42- -in in- -FPGA has taken over 300 design days up to now ! FPGA has taken over 300 design days up to now ! � � A lot of HW ! But minimal effort was spend for verification yet A lot of HW ! But minimal effort was spend for verification yet. . � � Visual inspection of simulations is cumbersome & erroneous ! Visual inspection of simulations is cumbersome & erroneous ! � � The purpose of a The purpose of a Regression Test Bench Regression Test Bench is to verify a design is to verify a design � versus a (target) Specification Specification (or a former stable state achieved). (or a former stable state achieved). versus a (target) � In our TVS In our TVS- -1 case the specification is the binary execution result 1 case the specification is the binary execution result � of a part of the original T425 instruction set. of a part of the original T425 instruction set. � The chosen instructions are the most important ones for a user The chosen instructions are the most important ones for a user � program (compiler) & can be verified by a simple IUT algorithm. program (compiler) & can be verified by a simple IUT algorithm. � Lesson learned Lesson learned : verifications takes as much effort than design! : verifications takes as much effort than design! � CPA 2017

  6. Transputer Verification Suite Transputer Verification Suite � TVS TVS- -1 1 *) *) uses a golden references based on real T425 outputs. uses a golden references based on real T425 outputs. � � Here: 54 IUT (instructions under test) with 1, 2 or 3 operands. Here: 54 IUT (instructions under test) with 1, 2 or 3 operands. � � IUT assembler code and sample set will be loaded into on IUT assembler code and sample set will be loaded into on- -chip chip � SRAMs before each run & comparison w/ golden reference file SRAMs before each run & comparison w/ golden reference file � Adaption for VHDL simulation was required: reduction of basic Adaption for VHDL simulation was required: reduction of basic � sample set from 128 *) *) to 32 values to achieve suitable run times. to 32 values to achieve suitable run times. sample set from 128 � Basic sample set contains 32 signed integers (32bit): corner ca Basic sample set contains 32 signed integers (32bit): corner cases ses � around MINT … … Zero Zero … … MaxInt, several bit MaxInt, several bit- -pattern and single pattern and single around MINT bit ‘ ‘1 1’ ’ and and ‘ ‘0 0’ ’ values, some small and large integers. values, some small and large integers. bit � Permutations: if Areg & Breg loaded then 32x32=1024 sets used. Permutations: if Areg & Breg loaded then 32x32=1024 sets used. � Info: *) TVS- -1 was written by 1 was written by Michael Bruestle Michael Bruestle in 2010 to support software in 2010 to support software Info: *) TVS development & verification of the Transputer Emulator Project ( Gavin Crate Gavin Crate ) ) development & verification of the Transputer Emulator Project ( CPA 2017

  7. TVS- -1 Coverage (Instructions) 1 Coverage (Instructions) TVS TVS- -1 covers 54 instructions: 1 covers 54 instructions: TVS ; load test � primary (3/16) ldc, adc, eqc, primary (3/16) ldc, adc, eqc, … … � ldl CREG � arithm. logic (16/17) add, gt, xor, arithm. logic (16/17) add, gt, xor, … … � ldl BREG � long arithmetic (9/9) ladd, lsum, long arithmetic (9/9) ladd, lsum, … … ldl AREG � � indexing (5/8) bsub, wcnt, indexing (5/8) bsub, wcnt, … … � __IUT__ � error handling (2/8) ccnt1, csub0, error handling (2/8) ccnt1, csub0, … … � stl AREG � general (7/8) csngl, xword, general (7/8) csngl, xword, … … � stl BREG � CRC and bits (5/5) bitcnt, CRC and bits (5/5) bitcnt, … … stl CREG � testerr � floating point (5/6) unpack, floating point (5/6) unpack, … … � stl ERROR � ALT (2/12) alt, talt. ALT (2/12) alt, talt. � ; send result 7 input files to meet different IUT requirements, 7 input files to meet different IUT requirements, e.g. for arithmetic, shift, range check, FP, … … e.g. for arithmetic, shift, range check, FP, CPA 2017

  8. TVS- -1 1 Coverage (Samples) Coverage (Samples) TVS TVS-1 input Extra Areg Breg Creg NO. of WORDs per SET IN-WORDs � TVS-1 original set Constants Values Values Values TESTs 128 BBBBBBBB CCCCCCCC TEST.1 i32_1.bin 128 3 384 (original) TEST.1.4 i32_1.bin 8 128 BBBBBBBB CCCCCCCC 1.024 3 3072 TEST.2 i32_2.bin 128 128 CCCCCCCC 16.384 3 49152 TEST.3 i32_3.bin 128 128 8 131.072 3 393216 TEST.B i32_B.bin 32 128 8 32.768 3 98304 TEST.F i32_F.bin 64 BBBBBBBB CCCCCCCC 64 3 192 TEST.P i32_P.bin 14 8 72 14 112.896 4 451584 TEST.S i32_S.bin 66 128 8 67.584 3 202752 361.920 Original TVS-1 has ~360.000 tests (can be used over link only … may be � later in case T42-in-FPGA is running on an FPGA board w/ PC connection) T42 TVS-1 will have ~25.000 tests (could be increased in case necessary) � TVS-1 Benefit : a TVS-1 run after (some) VHDL modifications will verify if the design still � meets the specification ... or: if there is any (bad) impact from recent changes CPA 2017

  9. TVS- -1 1 Coverage (Samples) Coverage (Samples) TVS TVS-1 input Extra Areg Breg Creg NO. of WORDs per SET IN-WORDs � TVS-1 (T-42) set Constants Values Values Values TESTs 128 BBBBBBBB CCCCCCCC TEST.1 i32_1.bin 128 3 384 for T42 TEST.1.4 i32_1.bin 8 128 BBBBBBBB CCCCCCCC 1.024 3 3072 TEST.2 i32_2.bin 32 32 CCCCCCCC 1.024 3 3072 TEST.3 i32_3.bin 32 32 8 8.192 3 24576 TEST.B i32_B.bin 32 32 2 2.048 3 6144 TEST.F i32_F.bin 64 BBBBBBBB CCCCCCCC 64 3 192 TEST.P i32_P.bin 10 8 10 10 8.000 4 32000 TEST.S i32_S.bin 32 32 4 4.096 3 12288 Output example: 24.576 prep_iut.BAT: IUT is ADC prepared @ 11.08.2017 11:46:43,65 tb_07_tvs1.vhd: simulation started... tb_07_tvs1.vhd: simulation Ok. - 4096.word - end of ..\sim\tb_07\golden_reference.mem reached. ghdl_sim.BAT: IUT is ADC finished @ 11.08.2017 11:47:11,96 ------------------------------------------------------------------------- prep_iut.BAT: IUT is ADD prepared @ 12.08.2017 12:05:46,48 tb_07_tvs1.vhd: simulation started... tb_07_tvs1.vhd: simulation Ok. - 16384.word - end of ../sim/tb_07/golden_reference.mem reached. modelsim.BAT: IUT is ADD finished @ 12.08.2017 12:13:25,95 CPA 2017

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