Slides for Lecture 6 ENCM 501: Principles of Computer Architecture Winter 2014 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 28 January, 2014
slide 2/33 ENCM 501 W14 Slides for Lecture 6 Previous Lecture ◮ introduction to ISA design ideas ◮ memory-register and load-store architectures ◮ a very brief history of RISC versus CISC ◮ aspects of the ISA view of memory—flat address spaces, alignment rules
slide 3/33 ENCM 501 W14 Slides for Lecture 6 Today’s Lecture ◮ endianness ◮ addressing modes ◮ examples of tradeoffs in instruction set design Related reading in Hennessy & Patterson: Sections A.3–A.7
slide 4/33 ENCM 501 W14 Slides for Lecture 6 Endianness This is not really an aspect of computer design in which there are interesting cost or performance tradeoffs. Rather, it’s an annoying detail that will occasionally bite you if you aren’t aware of it. Registers inside processor cores do not have endianness. An N -bit register just has bits N − 1 (MSB), N − 2, . . . , 2, 1, 0 (LSB). Endianness is a property of the interface between the processor core and the memory, and comes from the fact that most ISAs allow memory reads and writes with various sizes, typically 1-byte, 2-byte, 4-byte, and 8-byte.
slide 5/33 ENCM 501 W14 Slides for Lecture 6 Endianness in 64-bit MIPS doublewords The byte offset gives the address of an individual byte relative to the address of the entire doubleword. Bit numbering: 63 is MSB, 0 is LSB 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 +7 +6 +5 +4 +3 +2 +1 +0 LITTLE-endian byte offsets Bit numbering: 63 is MSB, 0 is LSB 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 +0 +1 +2 +3 +4 +5 +6 +7 BIG-endian byte offsets
slide 6/33 ENCM 501 W14 Slides for Lecture 6 Endianness in 32-bit MIPS words The byte offset gives the address of an individual byte relative to the address of the entire word. Bit numbering: 31 is MSB, 0 is LSB 31 24 23 16 15 8 7 0 +3 +2 +1 +0 LITTLE-endian byte offsets Bit numbering: 31 is MSB, 0 is LSB 31 24 23 16 15 8 7 0 +0 +1 +2 +3 BIG-endian byte offsets
slide 7/33 ENCM 501 W14 Slides for Lecture 6 Example effect of endianness in MIPS32 Assume that R8 contains some valid address that is a # LI: pseudoinstruction multiple of four. # for "load immediate" LI R9, 0x12345678 What goes into R10 , R11 , SW R9, 0(R8) R12 , R13 , if the processor LB R10, 0(R8) chip is in little-endian LB R11, 1(R8) mode? LB R12, 2(R8) What if the processor chip LB R13, 3(R8) is in big-endian mode?
slide 8/33 ENCM 501 W14 Slides for Lecture 6 Practical code rarely (if ever) writes data as a word and later reads it back as bytes, as was done in the example on the last slide. Why is endianness a practical concern? Here is a practical problem: ◮ Program P1 on Computer C1 copies an array of integers or FP numbers from memory into a file using a function like fwrite in the C library. ◮ On disk, the file is just a long sequence of bytes . ◮ Program P2 on Computer C2 opens the file and tries to read the array of numbers from the file into memory using a function like fread in the C library. ◮ But C2 does not have the same endianness as C1, so the data does not make sense to P2. The same kind of problem can happen when streaming multi-byte numbers over a network .
slide 9/33 ENCM 501 W14 Slides for Lecture 6 Endianness and real systems Today little-endianness is much more common than big-endianness. Here are some little-endian systems: ◮ anything running on x86 or x86-64; ◮ Apple iOS, Linux (including Android), and Windows running on ARM. Some historically important big-endian machines were: ◮ Macs with 68000- or PowerPC-based processors; ◮ 68000- and SPARC-based computers from Sun Microsystems. Many modern ISA families, for example, MIPS and ARM, allow the processor to switch back and forth between little- and big-endian modes.
slide 10/33 ENCM 501 W14 Slides for Lecture 6 Addressing modes Unlike endianness, selection of addressing modes for an ISA is a set of design decisions that involve interesting tradeoffs . Addressing mode is a slightly misleading term, because it refers to the way in which an operand is accessed by an instruction, and that might or might not involve generation of a memory address . Addressing modes for data access are discussed as part of Section A.3 in the textbook. Addressing modes for instruction access—needed, for example, by branches and jumps—are discussed in Section A.6.
slide 11/33 ENCM 501 W14 Slides for Lecture 6 Examples of addressing modes for data Figure A.6 in the textbook gives examples covering most addressing modes available in ISAs of the present and the recent past. A typical ISA will support some but not all of these addressing modes. (Historical note: I think the MC68000 series supported all of them and more, which is kind of awesome.) This lecture won’t explain every addressing mode in detail, but instead will look at the ones that are most common and important. Let’s start with the two modes that don’t involve generation of a memory address . . .
slide 12/33 ENCM 501 W14 Slides for Lecture 6 Addressing modes: Register and Immediate Register: Data is coming from or going to a register. All three operands are accessed in register mode in this MIPS64 instruction: DADDU R10, R8, R9 Immediate: Source data is a constant written into the instruction. Here is a MIPS64 example in which two operands are register-mode and one is immediate-mode: DADDIU R16, R16, 8
slide 13/33 ENCM 501 W14 Slides for Lecture 6 Encoding of immediate operands in example ISAs x86-64: Instruction size is variable, so 1, 2, 4, or 8 bytes are used, as necessary, to describe the constant. MIPS32 and MIPS64: Instructions are always 32 bits wide and the field size for immediate operands is always 16 bits wide. The range of constants is − 32768 to +32767 for instructions that use signed constants and 0 to 65535 for those that use unsigned constants. ARM: 12 bits within the fixed instruction size of 32 bits are used for an immediate operand, in a complicated and interesting way that could totally derail a lecture! (That’s one of a few very good reasons why it would not be easy to switch from MIPS to ARM in ENCM 369.)
slide 14/33 ENCM 501 W14 Slides for Lecture 6 The two simplest addressing modes for memory access Hint for comprehension: Roughly speaking, indirect means “via a pointer”. Register indirect: Use the bits in a register as a memory address. MIPS64 example: LD R8, (R9) # R8 = doubleword at address in R9 Displacement: Add a constant to the bits in a register to generate a memory address. MIPS64 example: # R10 = doubleword at address R10 + 64 bytes LD R10, 64(R11) Why is register indirect mode really just a special case of displacement mode?
slide 15/33 ENCM 501 W14 Slides for Lecture 6 Scaled mode: Good for array element access Here is some x86-64 assembly language code you will look at in Assignment 2 . . . .L16: mov (%rbx,%rax,4), %edx addq $1, %rax addq %rdx, %rbp cmpq $500000000, %rax jne .L16 The mov instruction uses scaled mode: The address used to read memory is %rbx + 4 × %rax %rbx is the address of element 0 of an array of 4-byte elements, and %rax is an index into that array.
slide 16/33 ENCM 501 W14 Slides for Lecture 6 Autoincrement and autodecrement modes (1) Other names for these modes are post-increment and pre-decrement . In either of these modes a load causes two register updates—one to a destination register, and another to a pointer register. A store also causes two updates—one update to a memory location and another to a pointer register. Both are useful for walking through arrays using pointer arithmetic . A store using pre-decrement mode is an efficient way to push a register value on to a stack . And a load using post-increment mode is an efficient way to pop a register value from a stack .
slide 17/33 ENCM 501 W14 Slides for Lecture 6 Autoincrement and autodecrement modes (2) These modes closely match some famously tricky C and C ++ expressions. Let’s write a couple of C statements that could be each be implemented using a single instruction if autoincrement and autodecrement modes are available.
slide 18/33 ENCM 501 W14 Slides for Lecture 6 Memory indirect mode Example, using syntax from textbook Figure A.6: MOV R0, @(R1) The address in R1 is used to read a second address from memory. That second address is used to read from memory into R0 . In a typical load/store architecture this would be done with two instructions: a load followed by another load . Another example, using the same syntax: MOV @(R2), R3 The address in R2 is used to read a second address from memory. That second address is used to write the data from R3 to memory. In a typical load/store architecture this would be done with two instructions: a load followed by a store . This mode is somewhat obsolete these days, but thinking about it helps to understand pointer-to-pointer types in C and C ++ .
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