Shaahin Hessabi Department of Computer Engineering Sharif University of Technology
Requirements Requirements � Design ‐ for ‐ reuse is necessary for both memories and analog circuits. � Both sensitive to noise and technology parameters. � Hence, hard cores or custom ‐ designed h d d i d � Design ‐ for ‐ reuse for these circuits requires items described for logic cores plus many additional rules and checks logic cores plus many additional rules and checks. 2 Sharif University of Technology Memory and Analog Cores
Why Large Embedded Memories? Why Large Embedded Memories? � 50 ‐ 60% of the SoC area is occupied by memories. � Multiple SRAMs, multiple ROMs, large DRAMs, flash memory blocks. � Modern microprocessors: more than 30% of the chip area is occupied by embedded cache. i d b b dd d h � Motivations of large embedded memories: Reduction in cost and size by integration of memory on the chip Reduction in cost and size by integration of memory on the chip. 1 1. On ‐ chip memory interface (replacing large off ‐ chip drivers with smaller 2. on ‐ chip drivers) reduces capacitive load, power, heat, length of wire. � achieving higher speeds. � Elimination of pad limitations of off chip modules and using a larger word Elimination of pad limitations of off ‐ chip modules and using a larger word 3 3. width. higher performance. � 3 Sharif University of Technology Memory and Analog Cores
The Increasing Memory Content The Increasing Memory Content 100% 20 90% 80% 80% 52 70% 71 60% Memory y 83 83 90 90 94 50% Reused Logic 40% New Logic 30% 20% 10% 10% 0% 1999 2002 2005 2008 2011 2014 4 Sharif University of Technology Memory and Analog Cores
Integration of Large Memory with Logic I i f L M i h L i � Adds significant complexity to g p y the fabrication process � Increases mask counts � affects cost and memory density � impacts total capacity, timing of peripheral circuits and system of peripheral circuits, and system performance. � If process optimized for logic p p g to obtain performance: � high saturation current prohibits a conventional one ‐ transistor ti l t i t DRAM cell. � the 4T cell: simple, good performance, large area 5 Sharif University of Technology Memory and Analog Cores
Integration of Large Memory with Logic I i f L M i h L i � If optimized for DRAM with p very low leakage current: � performance (switching speed) of the logic transistor suffers. f h l ff � 1T cell is used, which allows area optimization, but requires a p , q complex voltage regulator and dual ‐ gate process � Provides approximately half the � Provides approximately half the performance of previous scheme. 6 Sharif University of Technology Memory and Analog Cores
Integration of Large Memory with Logic Integration of Large Memory with Logic � Solution: dual ‐ gate processes � 2 different types of gate oxides optimized for DRAM and logic transistors. � logic and memory fabricated in different parts of the chip, each using its own set of technology parameters own set of technology parameters. � If flash memory used: double poly ‐ silicon layers required. 7 Sharif University of Technology Memory and Analog Cores
Basic Structures 6T SRAM 6T SRAM cell ll 4T DRAM cell 4T DRAM cell 3T DRAM cell 1T Flash cell 1T Flash cell 1T DRAM cell 8 Sharif University of Technology Memory and Analog Cores
B Basic Structures i St t 2 ‐ port memory 2 independent single ‐ ended reads or one differential write. 2 reads and one write by time multiplexing y p g Read during φ 1, write during φ 2 Content ‐ Addressable Memory (CAM) y ( ) Used in caches. Read and Write cycles: like before… Match c cle place data on bit lines but don’t Match cycle: place data on bit lines but dont assert word line. The word match lines from the CAM array can be used as WORD lines in a companion RAM to be used as WORD lines in a companion RAM to read out other data associated with the tag stored in the CAM. Uses: fully ‐ associative caches translation Uses: fully associative caches, translation lookaside buffers (TLBs), ... 9 Sharif University of Technology Memory and Analog Cores
M Memory Compiler C il � provide a framework that � provide a framework that includes physical, logical, and electrical representations of p the design database. � Linked with front ‐ end design tools and generate data that is readable with back ‐ end tools. 10 Sharif University of Technology Memory and Analog Cores
IP Generator/Compiler IP Generator/Compiler � User specifies � Power dissipation, code size, application performance, die size � Types, numbers and sizes of functional unit, including processor � User defined instructions � User ‐ defined instructions. � Tool generates � RTL code diagnostics and test reference bench � RTL code, diagnostics and test reference bench � Synthesis, P&R scripts � Instruction set simulator, C/C++ compiler, assembler, linker, debugger, profiler, initialization and self ‐ test code 11 Sharif University of Technology Memory and Analog Cores
T Trends for Mixed ‐ Signal SoCs d f Mi d Si l S C � Real world signals are analog � Real world signals are analog � Information processing and computing are in digital computing are in digital � Problem: Analog and digital circuits often don’t get along circuits often dont get along together! 12 Sharif University of Technology Memory and Analog Cores
The Substrate Crisis The Substrate Crisis 13 Sharif University of Technology Memory and Analog Cores
Digital Noise Coupling l l Fast transients in Switching noise in g digital circuits analog circuits Who needs to consider the substrate coupling noise impact? 14 Sharif University of Technology Memory and Analog Cores
Sources of Substrate Noise Sources of Substrate Noise � Inductive Noise (di/dt, 100 mV) � Bonding wires � Large di/dt on power supplies � Non ideal power supplies connecting directly to the substrate � Non ‐ ideal power supplies connecting directly to the substrate � Capacitive Coupling (dv/dt, 10 mV) � Interconnect capacitance to substrate � Interconnect capacitance to substrate � Junction capacitances � Impact Ionization (I drain , V gs & V ds , 2 mV) p ( drain , ds , ) gs � High electric field near the drain of saturated MOS devices � Substrate current injection 15 Sharif University of Technology Memory and Analog Cores
I d Inductive Noise ti N i � L changes with: � Type of package � Type of package � Number of pins for a connection 16 Sharif University of Technology Memory and Analog Cores
C Capacitive Noise iti N i � Large capacitance to substrate (supply, buses, output drivers, clock, etc.) , , ) � Shielding reduces some values 17 Sharif University of Technology Memory and Analog Cores
Primary Noise Sources Primary Noise Sources � Logic power rail bounce due to driver switching � Chip substrate coupling � Package resonance (excited by overtones of clock) � Analog power rail bounce � Noise coupling to various isolated device structures is proportional to the capacitance from that device to chip substrate. � No effective shielding techniques. � Separation of noise transmitter from noise receiver makes little difference in � S ti f i t itt f i i k littl diff i coupled noise due to low substrate resistance (for heavily doped substrate) � Noise is linear with switching power on ‐ chip. Noise is linear with switching power on chip. � Noise peak voltage increases as logic transitions are synchronized for a given amount of switching power. Noise energy unchanged. g g p gy g � Noise energy proportional to logic power rail inductance. 18 Sharif University of Technology Memory and Analog Cores
Primary Noise Sources (cont’d) Primary Noise Sources (cont d) � Synchronous noise � Using single clock for switching functions. � Can excite the package system resonance in phase with analog sampling clock clock. � Its effect can be a DC shift in the sampled signal with a given noise excitation level. � Pseudo ‐ synchronous noise � Mainly due to package resonance when excited by the CMOS switching. � If clock frequency is at the package resonant frequency the noise will increase dramatically One must lower the Q by increasing damping increase dramatically. One must lower the Q by increasing damping. � Asynchronous noise � Noise from mixing clocks Will start chip ‐ package ‐ PCB system resonating on � Noise from mixing clocks. Will start chip ‐ package ‐ PCB system resonating on the asynchronous clock edges. The asynchronous clocks will also couple this noise to the chip substrate and therefore to the analog circuits. 19 Sharif University of Technology Memory and Analog Cores
RF IC P RF IC Problem bl � Weak signals at RF input ( μ V) ( μ ) g p � Several on ‐ chip noise mechanisms must be controlled � Linear and non ‐ linear mixing and alaising with sampling of different noise sources � Coupled noise will manifest at different frequencies (e.g. Coupled noise will manifest at different frequencies (e.g. phase noise due to low frequency modulation of transistors) and analysis/simulation especially complicated. � Small signal conventional analysis may not be adequate. � High integration: both analog (like VCOs, A/D), and digital (A/D, DSP) may exists on the same chip. 20 Sharif University of Technology Memory and Analog Cores
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