Digital Testing Digital Testing Lecture 9 : Combinational - PowerPoint PPT Presentation

Digital Testing Digital Testing Lecture 9 : Combinational Automatic Test Pattern Automatic Test-Pattern Generation (ATPG) Basics Generation (ATPG) Basics Instructor: Shaahin Hessabi Instructor: Shaahin Hessabi Department of Computer Engineering Sharif University of Technology S U y gy Adapted with modifications from lecture notes prepared by the book authors Sharif University of Technology Testability: Lecture 9 1

Outline � Structural vs. functional test � C mpl t n � Completeness � Aspects of Test Generation � Test Generation Approaches � Ad-Hoc � Exhaustive testing � Fault table analysis � Boolean difference method � Boolean difference method � (Pseudo) random test generation � Fault-oriented deterministic methods � Fault-independent deterministic methods Sharif University of Technology Testability: Lecture 9 Slide 2 of 45

Origins of Stuck Faults Origins of Stuck-Faults � Eldred (1959) – First use of structural testing for the Honeywell Datamatic 1000 computer y p � Galey, Norby, Roth (1961) – First publication of stuck-at-0 and stuck-at-1 faults stuck-at-0 and stuck-at-1 faults � Seshu & Freeman (1962) – Use of stuck-faults for parallel fa lt sim lation for parallel fault simulation � Poage (1963) – Theoretical analysis of stuck-at f faults l Sharif University of Technology Testability: Lecture 9 Slide 3 of 45

Functional vs. Structural ATPG F ti l St t l ATPG Sharif University of Technology Testability: Lecture 9 Slide 4 of 45

Carry Circuit Carry Circuit Sharif University of Technology Testability: Lecture 9 Slide 5 of 45

Functional vs Structural(Cont’d) Functional vs. Structural(Cont’d) � Functional ATPG: generate complete set of tests for circuit g p input-output combinations. For the adder example: � 129 inputs, 65 outputs: � 2 129 = 680 564 733 841 876 926 926 749 214 863 536 422 912 patterns � 2 129 = 680,564,733,841,876,926,926,749,214,863,536,422,912 patterns � Using 1 GHz ATE, would take 2.15 x 10 22 years � Structural test: � No redundant adder hardware, 64 bit slices � Each with 27 faults (using fault equivalence) � At most 64 x 27 = 1728 faults (tests) ( ) � Takes 0.000001728 (1.7 μ sec) on 1 GHz ATE � Designer gives small set of functional tests; augment with structural tests to boost coverage to 98 + % t 98 + % t t l t t t b t Sharif University of Technology Testability: Lecture 9 Slide 6 of 45

Definition of Automatic Test-Pattern Generator � Operations on digital hardware: � Operations on digital hardware: � Inject fault into circuit modeled in computer � Use various ways to activate and propagate fault effect through hardware to circuit output h d t i it t t � Output flips from expected to faulty signal � Electron-beam ( E-beam ) test observes internal signals: � Electron beam ( E beam ) test observes internal signals: “picture” of nodes charged to 0 and 1 in different colors � Too expensive � Scan design: add test hardware to all flip-flops to make them a giant shift register in test mode � C � Can shift state in, scan state out hift t t i t t t � Widely used; makes sequential test combinational � Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence p y p g q Sharif University of Technology Testability: Lecture 9 Slide 7 of 45

Circuit and Binary Decision Tree Sharif University of Technology Testability: Lecture 9 Slide 8 of 45

Binary Decision Diagram Binary Decision Diagram � BDD – Follow path from source to sink node – product of literals along path gives Boolean value at sink � Rightmost path: A B C = 1 � Problem: Size varies greatly with variable order with variable order Sharif University of Technology Testability: Lecture 9 Slide 9 of 45

Algorithm Completeness go t Co p ete ess � Definition: Algorithm is c omplete if it ultimately � Definition: Algorithm is c omplete if it ultimately can search entire binary decision tree, as needed, to generate a test to generate a test � Untestable fault : no test for it, even after entire tree searched tree searched � Combinational circuits only: untestable faults are redundant, showing the presence of unnecessary d d h i h f hardware Sharif University of Technology Testability: Lecture 9 Slide 10 of 45

Combinational Test Generation Combinational Test Generation � We discuss testing for SSF with the following assumptions: off-line , edge-pin , stored-pattern testing with full comparison of the output results. � Given � a logical fault model, � and a circuit, determine � a small set of test vectors that detects all faults in the circuit. � Under the stuck-at fault model, the problem is NP- p complete for combinational circuits � However, test generators that efficiently generate tests for 1M-gate circuits are in use today. Sharif University of Technology Testability: Lecture 9 Slide 11 of 45

Test Generation Process Sharif University of Technology Testability: Lecture 9 Page 12 of 41

Aspects of Test Generation Aspects of Test Generation 1 1. The cost of TG The cost of TG � Depends on the complexity of the TG method; e.g., Random TG (RTG) is simple. However: Needs a large set of random vectors to achieve high fault a. coverage. The required fault simulation might be an expensive process expensive process. Longer test ⇒ Higher cost to apply (increases time of testing b. equipment, and memory requirement for tester). � Random vectors are often generated on-line by hardware and used with compact testing. � � TG cost also depends on the complexity of CUT TG cost also depends on the complexity of CUT. DFT techniques reduce the CUT complexity for testing � purposes. Sharif University of Technology Testability: Lecture 9 Slide 13 of 45

Aspects of Test Generation (cont’d) Aspects of Test Generation (cont’d) 2. The quality of the generated test � � Normally measured by fault coverage determined by fault Normally measured by fault coverage, determined by fault simulation. � Deterministic TG produces shorter and higher-quality tests (w.r.t. RTG), by taking into account the function or the structure of the CUT. 3. The cost of applying the test (time and memory 3 Th t f l i th t t (ti d requirements of the tester) Sharif University of Technology Testability: Lecture 9 Slide 14 of 45

Test Generation Approaches Test Generation Approaches 1 1. Ad-Hoc Ad-Hoc 2. Exhaustive testing 3. Fault table analysis 4. Boolean difference method 5. (Pseudo) random test generation 6. 6 Fault-oriented deterministic methods: Fault oriented deterministic methods: a. D-algorithm [Roth 1968] b. PODEM [Goel 1981] [ ] 7. Fault-independent deterministic methods: � Critical path method p Sharif University of Technology Testability: Lecture 9 Slide 15 of 45

1. Ad-Hoc � Uses functional test vectors developed by designers for functional verification and design debugging by: functional verification and design debugging by: � Fault simulating to determine fault coverage � Determining locations of undetected faults � Adding additional functional tests to exercise areas of design with undetected faults � Re-fault simulating and repeating until desired fault coverage is g g g achieved � No special test generation system is required, only fault simulator i l � Utilizes existing vectors and designer expertise � Achieving high fault coverage may be difficult and time consuming, specially for synthesized designs. Sharif University of Technology Testability: Lecture 9 Slide 16 of 45

2. Exhaustive Testing 2. Exhaustive Testing � Applying all possible 2 n possible input patterns pp y g p p p p � Satisfactory for small circuits only. Infeasible, unless circuit is partitioned into cones of logic, with less than 15 inputs (pseudo- exhaustive testing) exhaustive testing) � Perform exhaustive ATPG for each cone � Misses faults that require specific activation patterns for multiple cones to be tested � Assuming a tester capable of applying a test pattern every 100ns (10 MHz), we can calculate the test time as l l h shown in table 1. Sharif University of Technology Testability: Lecture 9 Slide 17 of 45

2 Exhaustive Testing (cont’d) 2. Exhaustive Testing (cont d) Inputs Inputs # of Tests # of Tests Test Time Test Time 2 20 ≈ 10 6 20 0.1 sec 2 40 ≈ 10 12 40 30.5 hours 2 60 ≈ 10 19 60 58500 years Sharif University of Technology Testability: Lecture 9 Slide 18 of 45

3. Fault Table Analysis y Fault Table example Sharif University of Technology Testability: Lecture 9 Page 19 of 41

Fault Table Analysis (cont’d) Fault Table Analysis (cont d) Reduced fault table after d d b “fault collapsing” Conclusion: 5 tests are needed of which 3 are needed, of which, 3 are essential. Sharif University of Technology Testability: Lecture 9 Page 20 of 41