Digital Testing g g Lecture 5: Fault Modeling Instructor: Shaahin - - PowerPoint PPT Presentation
Digital Testing g g Lecture 5: Fault Modeling Instructor: Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Adapted with modification from lecture notes prepared by the
The testing problem Wh
Why model faults? Some real defects in VLSI and PCB
Common fault models Stuck-at faults
Si l k f l
Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults
Transistor faults Summary
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Costs increase dramatically as faulty components find their
Test: Apply a set of vectors to each device off the
The optimum test set will detect the greatest number of
Types of test sets:
Exhaustive: apply every possible input vector.
F i l f i f h d i
Functional: test every function of the device. Fault-Model Derived: find a test for every “modeled” fault.
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Exhaustive testing
Will detect 100% of detectable faults
i
14
Requires 214 = 16,384 test vectors A 16 bit ALU with 38 inputs would take 7.64 hours to exhaustively test at
10 MHz
Functional testing
Will detect 100% of detectable faults
T t l f ti l t ti ill t k 448 t
Total functional testing will take over 448 vectors
Each logical mode can be tested with about 8 vectors Each arithmetic mode can be tested with about 20 vectors
There is no algorithmic way to verify that all functional modes have been
tested (designer expertise required)
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Modeled fault testing (e.g. single stuck faults)
Will detect 100% of detectable modeled faults Requires only 47 vectors Vectors can be generated and analyzed (for fault coverage) using Vectors can be generated and analyzed (for fault coverage) using
computer programs
The number of defects actually detected by this test vector set depends on
the quality of the fault model
The key is to select a fault model that can be applied to the appropriate
level of circuit abstraction (logic level) and that maps to the most possible level of circuit abstraction (logic level) and that maps to the most possible physical defects
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I/O function tests inadequate for manufacturing
Real defects (often mechanical) too numerous and often
A fa lt model identifies targets for testing A fault model identifies targets for testing A fault model makes analysis possible Eff
Effectiveness measurable by experiments
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B lk d f t ( k t l i f ti )
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - S i d t D i d Ci it Wil 1981
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Semiconductor Devices and Circuits, Wiley, 1981.
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Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.
Single stuck-at faults
Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults Bridging faults …
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1.
2.
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Referred to as the classical fault model Most widely studied and used
y
It represents many different physical faults It is independent of technology Experience has shown that tests that detect SSFs detect many non-
classical faults as well
The number of SSFs in a circuit is small. The number of SSFs in a circuit is small.
– Moreover, the number of faults to be explicitly analyzed can be reduced by fault collapsing techniques.
If h li hi h SSF b d fi d h b f ibl
If there are n lines on which SSFs can be defined, the number of possible
faults is 2n. – We need to consider every fanout branch as a separate line
y p – The total number of SSFs ~ 2Gf G : # of gates f : the average fan out count
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f : the average fan-out count
Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults
c j Good circuit value Faulty circuit value a c d
1
g h
s-a-0
j z
0(1) 1(0)
b e f i
1
k z
1
f Test vector for h s-a-0 fault
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Important in high density circuits A multiple stuck-at fault means that any set of lines is
The total number of single and multiple stuck-at faults in
A single fault test can fail to detect the target fault if
Statistically, single fault tests cover a very large number of
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Stuck fault on I/O connection of a module Exclusive-OR gate:
6 pin faults:
a/0 a/1 b/0 b/1 Z/0 Z/1 a/0, a/1, b/0. b/1, Z/0, Z/1
100% pin fault coverage:
{ab= 00, 01, 10} or {ab= 01, 10, 11} or {ab= 00, 01, 11} or {ab= 00, 10, 11}
100% flattened fault coverage:
Requires all 4 vectors Requires all 4 vectors
a c d z a b d e
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f
Number of fault sites in a Boolean gate circuit
Fault equivalence: Two faults f1 and f2 are equivalent if all
If faults f1 and f2 are equivalent then the corresponding faulty functions
are identical (functional equivalent).
Fault collapsing: All single faults of a logic circuit can be
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sa0 sa0 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa1 sa1 AND OR WIRE sa0 sa1 sa0 sa1 1 AND OR sa0 sa0 sa1 sa1 NOT sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 NAND NOR sa0 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa0 sa1 sa1 FANOUT
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sa0 sa1 sa0 sa1 sa0 sa1 Faults in red removed by equivalence ll i sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1
collapsed faults
sa0 sa1 sa0 sa1 20 Collapse ratio = = 0 625
collapsed faults Sharif University of Technology
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Collapse ratio = ----- = 0.625 32
If all tests of some fault F1 detect another fault F2, then F2 is
Dominance fault collapsing: If fault F2 dominates F1, then F2
When dominance fault collapsing is used, it is sufficient to
In a tree circuit (without fan-outs) PI faults form a
If two faults dominate each other then they are equivalent.
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All tests for F2 s-a-1 F1 F2 001 All tests for F2 s-a-1 110 010 000 101 011 100 Only test for F1 s a 1 Only test for F1 s-a-1 s-a-1 1 s-a-1 s-a-0 A dominance collapsed fault set
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A dominance collapsed fault set
Primary inputs and fan-out branches of a combinational
Checkpoint theorem: A test set that detects all single
Total fault sites = 16 Total fault sites = 16 Checkpoints ( ) = 10
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Following classes of single stuck-at faults are identified by
Potentially-detectable fault -- Test produces an unknown (X) state at
primary output (PO) of a sequential circuit; detection is probabilistic, ll i h 50% b bili usually with 50% probability.
Initialization fault -- Fault prevents initialization of the faulty circuit; can
be detected as a potentially-detectable fault. p y
Hyperactive fault -- Fault induces much internal signal activity without
reaching PO. R d d f l N i f h f l
Redundant fault -- No test exists for the fault. Untestable fault -- Test generator is unable to find a test.
Superset of redundant faults in sequential circuits. Similar to redundant faults in combinational circuits.
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X3/1, X1/0, X2/0: untestable
Either M or N always 0 X3 always 1 Output can be taken from G instead of F
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Cannot set 1 on both inputs to the OR gate Untestable fault
OR changed to XOR
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Hazard elimination redundancy
Problem: output changes when A changes while BC = 11 Solution: intentional redundant implication BC
U t
Untestable fault: e/0
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Fault-free decoder
Only one output =1
E
E = 0
E/0 untestable if no fault in
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C/1 untestable
Z AB + ABC AB
Z = AB + ABC = AB
Testable fault A1/0 (ABC = 110)
Untestable in presence of the untestable fault C/1
p
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T d f i it h t d t th
1.
Bridging within a logic element (transistor gates, sources, or drains shorted together)
2.
Bridging between logic nodes (i.e., inputs or outputs of logic elements) without feedback
g
3.
Bridging between logic nodes with feedback
i ll id d i b id i f l i l d b
logic elements (transistor shorts across logic elements)
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C l t f h i l d f t h i di t
that BFs account for up to 30% of all defects
two bridged nodes to opposite values and observing the effect
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Th l i f ti f th CUT i f
delays in the CUT greater than some defined bounds y g
1.
Gate delay, or transitional fault model
2.
Path delay fault model
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fault, and SSF testing techniques can be applied.
detection (propagation)
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a faulty gate may be compensated for by other faster gates in the path
developed
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MOS transistor is considered an ideal switch and two types
Stuck-open: a single transistor is permanently stuck in the open state. Stuck-short: a single transistor is permanently shorted irrespective of its
gate voltage.
Detection of a stuck-open fault requires two vectors Detection of a stuck open fault requires two vectors. Detection of a stuck-short fault requires the measurement
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Vector 1: test for A s-a-0 (I iti li ti t )
pMOS (Initialization vector) Vector 2 (test for A s-a-1) Two-vector s-open test can be constructed by
DD
pMOS FETs 1 g
Stuck-
1
1(Z) nMOS FET Good circuit states F lt i it t t
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FETs Faulty circuit states
Advantages
C h i l d f d b k f l d l
Covers physical defects not covered by stuck-at fault model Can be tested with sequences of stuck-at fault test
Disadvantages Disadvantages
Requires a large number of tests (sequence for each fault) Algorithms for ATPG and fault simulation are more complex and less
g p well developed
Requires a lower level circuit description (transistor level), at least for
development of the fault list development of the fault list
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pMOS Test vector for A s-a-0
DD
pMOS FETs St k 1 IDDQ path in faulty circuit
Stuck- short 1 G d i it t t
0 (X) Good circuit state nMOS FET Faulty circuit state
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FETs Faulty circuit state
Fault models are analyzable approximations of defects and are
For digital logic, single stuck-at fault model offers best
Many other faults (bridging stuck open and multiple stuck Many other faults (bridging, stuck-open and multiple stuck-
Stuck-short and delay faults are technology-dependent faults
Memory and analog circuits need other specialized fault
Current practice
Single stuck at faults Single stuck-at faults Some simple gate delay faults Pattern-sensitive faults (memory only)
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