Digital Testing g g Lecture 5: Fault Modeling Instructor: Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Adapted with modification from lecture notes prepared by the Adapted, with modification, from lecture notes prepared by the book authors
Outline � The testing problem � Wh � Why model faults? d l f l ? � Some real defects in VLSI and PCB � Common fault models C f l d l � Stuck-at faults � Single stuck-at faults Si l k f l � Fault equivalence � Fault dominance and checkpoint theorem � Fault dominance and checkpoint theorem � Classes of stuck-at faults and multiple faults � Transistor faults � Summary Testability: Lecture 5 Sharif University of Technology Page 2 of 37
The Testing Problem � Costs increase dramatically as faulty components find their way into higher levels of integration (rule-of-10) way into higher levels of integration (rule of 10). � Test: Apply a set of vectors to each device off the manufacturing line and compare outputs to the known good g p p g response. � The optimum test set will detect the greatest number of p g defects that can be present in a device with the least number of test vectors (high defect coverage). � Types of test sets: � Exhaustive: apply every possible input vector. � Functional: test every function of the device. F i l f i f h d i � Fault-Model Derived: find a test for every “modeled” fault. Testability: Lecture 5 Sharif University of Technology Page 3 of 37
Testing Which type is closest to optimum Which type is closest to optimum Consider a 74181 ALU chip- 14 inputs p p � Exhaustive testing � Will detect 100% of detectable faults � Requires 2 14 = 16,384 test vectors 14 i � A 16 bit ALU with 38 inputs would take 7.64 hours to exhaustively test at 10 MHz � Functional testing � Will detect 100% of detectable faults � Total functional testing will take over 448 vectors T t l f ti l t ti ill t k 448 t � Each logical mode can be tested with about 8 vectors � Each arithmetic mode can be tested with about 20 vectors � There is no algorithmic way to verify that all functional modes have been tested (designer expertise required) Testability: Lecture 5 Sharif University of Technology Page 4 of 37
Which type is closest to optimum (cont’d) yp p ( ) � Modeled fault testing (e.g. single stuck faults) � Will detect 100% of detectable modeled faults � Requires only 47 vectors � Vectors can be generated and analyzed (for fault coverage) using � Vectors can be generated and analyzed (for fault coverage) using computer programs � The number of defects actually detected by this test vector set depends on the quality of the fault model � The key is to select a fault model that can be applied to the appropriate level of circuit abstraction (logic level) and that maps to the most possible level of circuit abstraction (logic level) and that maps to the most possible physical defects Testability: Lecture 5 Sharif University of Technology Page 5 of 37
Why Model Faults? y � I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) � Real defects (often mechanical) too numerous and often R l d f ( f h i l) d f not analyzable � A fa lt model identifies targets for testing � A fault model identifies targets for testing � A fault model makes analysis possible � Eff � Effectiveness measurable by experiments ti bl b i t Testability: Lecture 5 Sharif University of Technology Page 6 of 37
Some Real Defects in Chips � Processing defects � Missing contact windows � Parasitic transistors � Oxide breakdown . . . � � Material defects � B lk d f Bulk defects (cracks, crystal imperfections) t ( k t l i f ti ) Surface impurities (ion migration) � � . . . � Time dependent failures � Time-dependent failures � Dielectric breakdown Electromigration � � . . . � Packaging failures Contact degradation � � Seal leaks � . . . Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. S i d t D i d Ci it Wil 1981 Testability: Lecture 5 Sharif University of Technology Page 7 of 37
Observed PCB Defects Occurrence frequency (%) Occurrence frequency (%) Defect classes Defect classes 51 Shorts Shorts 1 Opens 6 Missing components 13 Wrong components 6 Reversed components 8 8 Bent leads Bent leads 5 Analog specifications 5 Digital logic g g 5 Performance (timing) Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. Testability: Lecture 5 Sharif University of Technology Page 8 of 37
Common Fault Models � Single stuck-at faults � Transistor open and short faults T i d h f l � Memory faults � PLA faults (stuck-at, cross-point, bridging) � Functional faults (processors) � Delay faults (transition, path) � Analog faults � Bridging faults � … Testability: Lecture 5 Sharif University of Technology Page 9 of 37
Single Stuck Faults g Structural logic-level fault model g Assumptions Only one line is faulty y y 1. Faulty line permanently set to 0 or 1 2. Fault can be at an input or output of a gate � 3. The function of the gates in the circuit is not affected by the fault Testability: Lecture 5 Sharif University of Technology Page 10 of 37
Single Stuck-at Fault � Referred to as the classical fault model � Most widely studied and used y � It represents many different physical faults � It is independent of technology � Experience has shown that tests that detect SSFs detect many non- classical faults as well � The number of SSFs in a circuit is small. � The number of SSFs in a circuit is small. – Moreover, the number of faults to be explicitly analyzed can be reduced by fault collapsing techniques. � If there are n lines on which SSFs can be defined, the number of possible li If h hi h SSF b d fi d h b f ibl faults is 2 n . – We need to consider every fanout branch as a separate line y p – The total number of SSFs ~ 2 Gf G : # of gates f : the average fan out count f : the average fan-out count Testability: Lecture 5 Sharif University of Technology Page 11 of 37
Single Stuck-at Fault g � Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value c c j j 0(1) s-a-0 d a 1(0) g h 1 z z i 0 1 e b 1 k f f Test vector for h s-a-0 fault Testability: Lecture 5 Sharif University of Technology Page 12 of 37
Multiple Stuck-at Faults p � Important in high density circuits � A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. � The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3 k -1. � A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fa lt b another is rare one fault by another is rare. � Statistically, single fault tests cover a very large number of multiple faults multiple faults. Testability: Lecture 5 Sharif University of Technology Page 13 of 37
Pin Faults � Stuck fault on I/O connection of a module � Exclusive-OR gate: � 6 pin faults: a/0 a/1 b/0 b/1 Z/0 Z/1 a/0, a/1, b/0. b/1, Z/0, Z/1 � 100% pin fault coverage: {ab= 00, 01, 10} or {ab= 01, 10, 11} or {ab= 00, 01, 11} or {ab= 00, 10, 11} � 100% flattened fault coverage: � Requires all 4 vectors � Requires all 4 vectors c d d a a z e b f Testability: Lecture 5 Sharif University of Technology Page 14 of 37
Fault Equivalence � Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). #PI #gates # (fanout branches). � Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2, and vice-versa. , � If faults f1 and f2 are equivalent then the corresponding faulty functions are identical (functional equivalent). � Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent A collapsed fault set contains subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. Testability: Lecture 5 Sharif University of Technology Page 15 of 37
Equivalence Rules q sa0 sa0 sa1 sa1 sa0 sa1 sa0 sa1 WIRE sa0 sa1 sa0 sa1 AND AND OR OR sa0 sa1 sa0 sa1 sa0 0 sa1 1 NOT sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 NAND NOR sa1 sa0 sa0 sa0 sa1 sa0 sa1 sa1 sa0 sa1 FANOUT Testability: Lecture 5 Sharif University of Technology Page 16 of 37
Equivalence Example q p sa0 sa1 Faults in red sa0 sa1 removed by sa0 sa1 equivalence collapsing ll i sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 collapsed faults collapsed faults sa0 sa1 sa0 sa1 20 Collapse ratio = Collapse ratio = ----- = 0.625 = 0 625 32 Testability: Lecture 5 Sharif University of Technology Page 17 of 37
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