Overview Motivation ECE 553: TESTING AND Fault Modeling - PDF document

9/9/2014 Overview • Motivation ECE 553: TESTING AND • Fault Modeling TESTABLE DESIGN OF – Why model faults? – Some real defects in VLSI and PCB – Some real defects in VLSI and PCB DIGITAL SYSTES DIGITAL SYSTES – Common fault models – Stuck-at faults – Transistor faults • Summary Fault Modeling 9/9/2014 2 Motivation Why Model Faults? – Models are often easier to work with • I/O function tests inadequate for manufacturing – Models are portable (functionality versus component and interconnect testing) – Models can be used for simulation, thus • Real defects (often mechanical) too numerous • Real defects (often mechanical) too numerous avoiding expensive hardware/actual circuit avoiding expensive hardware/actual circuit and often not analyzable implementation • A fault model identifies targets for testing – Nearly all engineering systems are studied • A fault model makes analysis possible using models • Effectiveness measurable by experiments – All the above apply for logic as well as for fault modeling 9/9/2014 3 9/9/2014 4 Some Real Defects in Chips Common Fault Models  Processing defects  Missing contact windows  Parasitic transistors • Single stuck-at faults  Oxide breakdown  . . . • Transistor open and short faults  Material defects  Bulk defects (cracks, crystal imperfections) • Memory faults  Surface impurities (ion migration)  . . . • PLA faults (stuck-at, cross-point, bridging)  Time-dependent failures p  Dielectric breakdown • FPGA faults (truthtable change)  Electromigration  NBTI (negative bias temperature instability) • Functional faults (processors)  . . .  • Delay faults (transition, path) Packaging failures  Contact degradation • Analog faults  Seal leaks  . . . • For more examples, see Section 4.4 (p. 60-70) of Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - the book. Semiconductor Devices and Circuits, Wiley, 1981. + more recent defect types 9/9/2014 5 9/9/2014 6 1

9/9/2014 Single Stuck-at Fault Stuck-at Faults • Three properties define a single stuck-at fault • Only one line is faulty • The faulty line is permanently set to 0 or 1 • Single stuck-at faults • The fault can be at an input or output of a gate • What does it achieve in practice? • Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults single stuck-at faults • Fault equivalence F lt i l F Faulty circuit value lt i it l Good circuit value • Fault dominance and checkpoint c j 0(1) s-a-0 theorem d a 1(0) g h 1 z • Classes of stuck-at faults and multiple i 0 1 e b 1 faults k f Test vector for h s-a-0 fault 9/9/2014 7 9/9/2014 8 Single Stuck-at Faults (contd.) Fault Equivalence • Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). • How effective is this model? • Fault equivalence: Two faults f1 and f2 are equivalent –Empirical evidence supports the use if all tests that detect f1 also detect f2. of this model f thi d l • If faults f1 and f2 are equivalent then the If f lt f1 d f2 i l t th th corresponding faulty functions are identical. –Has been found to be effective to • Fault collapsing: All single faults of a logic circuit can detect other types of fauls be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed –Relates to yield modeling fault set contains one fault from each equivalence –Simple to use subset. 9/9/2014 9 9/9/2014 10 Equivalence Rules Equivalence Example sa0 sa0 sa0 sa1 Faults in red sa1 sa1 sa0 sa1 removed by sa0 sa1 sa0 sa1 sa0 sa1 WIRE equivalence sa0 sa1 sa0 sa1 collapsing AND OR sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 NOT sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa0 sa1 NAND NOR sa0 sa1 sa1 sa0 sa0 sa1 sa0 sa1 sa0 sa1 sa1 sa0 20 Collapse ratio = ----- = 0.625 sa1 32 FANOUT 9/9/2014 11 9/9/2014 12 2

9/9/2014 Fault Dominance Dominance Example • If all tests of some fault F1 detect another fault F2, then All tests of F2 F2 is said to dominate F1. F1 s-a-1 001 • Dominance fault collapsing: If fault F2 dominates F1, F2 110 010 s-a-1 then F2 is removed from the fault list. 000 101 011 • When dominance fault collapsing is used it is sufficient When dominance fault collapsing is used, it is sufficient 100 to consider only the input faults of Boolean gates. See the next example. Only test of F1 s-a-1 • In a tree circuit (without fanouts) PI faults form a s-a-1 dominance collapsed fault set. s-a-1 • If two faults dominate each other then they are s-a-0 equivalent. A dominance collapsed fault set 9/9/2014 13 9/9/2014 14 Checkpoints Classes of Stuck-at Faults • Primary inputs and fanout branches of a • Following classes of single stuck-at faults are combinational circuit are called checkpoints . identified by fault simulators: • Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a • Potentially-detectable fault -- Test produces an unknown (X) state at primary output (PO); detection is combinational circuit, also detects all single probabilistic usually with 50% probability probabilistic, usually with 50% probability. ( (multiple) stuck-at faults in that circuit. l i l ) k f l i h i i • Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable Total fault sites = 16 fault. • Hyperactive fault -- Fault induces much internal signal Checkpoints ( ) = 10 activity without reaching PO. • Redundant fault -- No test exists for the fault. • Untestable fault -- Test generator is unable to find a test. 9/9/2014 15 9/9/2014 16 Transistor (Switch) Faults Multiple Stuck-at Faults • A multiple stuck-at fault means that any set of lines • MOS transistor is considered an ideal switch and is stuck-at some combination of (0,1) values. two types of faults are modeled: • The total number of single and multiple stuck-at • Stuck-open -- a single transistor is permanently stuck in the open faults in a circuit with k single fault sites is 3 k -1. state. • Stuck-short -- a single transistor is permanently shorted St k h t i l t i t i tl h t d • A single fault test can fail to detect the target fault if irrespective of its gate voltage. another fault is also present, however, such masking • Detection of a stuck-open fault requires two vectors. of one fault by another is rare. • Detection of a stuck-short fault requires the • Statistically, single fault tests cover a very large measurement of quiescent current (I DDQ ). number of multiple faults. 9/9/2014 17 9/9/2014 18 3

9/9/2014 Stuck-Open Example Stuck-Short Example Vector 1: test for A s-a-0 (Initialization vector) Test vector for A s-a-0 Vector 2 (test for A s-a-1) pMOS pMOS V DD V DD Two-vector s-op test FETs FETs I DDQ path in can be constructed by faulty circuit A A ordering two s-at tests g A A St Stuck- k 1 1 0 0 1 1 Stuck- short open B B Good circuit state 0 0 0 C C 0 1(Z) 0 (X) Good circuit states nMOS nMOS Faulty circuit state FETs FETs Faulty circuit states 9/9/2014 19 9/9/2014 20 Summary • Fault models are analyzable approximations of defects and are essential for a test methodology. • For digital logic single stuck-at fault model offers best advantage of tools and experience. • Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. g y y • Stuck-short and delay faults and technology-dependent faults require special tests. • Memory and analog circuits need other specialized fault models and tests. 9/9/2014 21 4