= Sequential logic: elements to store values Output depends on inputs - PowerPoint PPT Presentation

Bistable latches Latch: CC-BY Rberteig@flickr Suppose we somehow get a 1 (or a 0?) on here. Q Q Latches, Flip-flops, Registers, Memory = Sequential logic: elements to store values Output depends on inputs and stored values . 0 0 Q Q (vs. combinational logic: output depends only on inputs) SR latch SR latch S R Q Q' Q (stable) Q' (stable) Q R 0 0 0 0 ? ? 0 0 0 1 0 1 0 0 1 0 1 0 Q S 0 0 1 1 ? ? R Q R 1 0 ? ? 1 0 Q 0 1 ? ? 0 1 Q Q S S Set Reset S R S R R Q Q Q Q Q Q S

Time matters! D latch R D D Q Data bit C Q C S Clock Q if C = 0 , then SR latch stores current value of Q. if C = 1 , then D flows to Q: if D = 0 , then R = 1 and S = 0, Q = 0 if D = 1 , then R = 0 and S = 1 , Q = 1 Clocks D flip-flop with falling-edge trigger leader follower Clock : free-running signal E with fixed cycle time = clock period = T. D Q Q F D L Q L D F Clock frequency = 1 / clock period D latch D latch Q Q F C L Q L C F Falling edge C Rising edge Clock period A clock controls when to update Can still read Q now Q next becomes Q now a sequential logic element's state. folower stores E as Q Clock leader stores D as E Time

Time matters! Reading and writing in the same cycle D D Q D Flip-Flop Assume Q is initially 0. Clock C Q C E Q *Half a byte! Register file A 1-nybble* register (a 4-bit hardware storage cell) Read register 0 D Q r selector 1 D Flip-Flop Read register Read data 1 C Q w r selector 2 Read ports D Q 1 Why 2? D Flip-Flop Read data 2 Write register w C Q r selector 0 D Q Write data D Flip-Flop w C Q Write port Write? 1 D Q 0 = read D Flip-Flop Write 1 = write r = log 2 number of registers C Q w = bits in word Clock Array of registers, with register selectors, write/read control, input port for writing data, output ports for reading data.

Write port (data in) Read register number 1 write control Register 0 clock Write Read ports Register 1 M C (data out) u . . . Read data 1 0 Register 0 1 x Register n – 2 D n -to-2 n . register number . Register number . decoder C Register n – 1 Register 1 n – 2 D n – 1 Read register number 2 . . . C M Register n – 2 u Read data 2 D x C Register n – 1 incoming data Register data D RAM (Random Access Memory) 16 x 4 RAM 4-bit address 1101 A B 4 to 16 decoder data out Similar to register file, except… 20