Roll-to-roll manufacture of organic transistors for low cost - PowerPoint PPT Presentation

Roll-to-roll manufacture of organic transistors for low cost circuits Hazel Assender Dr Gamal Abbas, Ziqian Ding Department of Materials University of Oxford DALMATIAN TECHNOLOGY 1 1 21 st Sept 2011

Acknowledgements Bangor Leeds Prof Martin Taylor Prof Long Lin Aled Williams Dr Weidong He Eifion Patchett Manchester Oxford Prof Steve Yeates Dr Kanad Mallik Dr John Morrison 2 2 21 st Sept 2011

Flagship project Can we manufacture transistors/simple circuits from organic materials using R2R vacuum evaporation processes? Need to consider: 1) Process parameters in R2R environment – building and testing transistors 2) Circuit design tailored for the properties achievable with this manufacturing route 3) Materials (semiconductor and gate insulator layer) developed for this manufacturing route 4) Patterning processes 5) Robustness of final devices 3 3 21 st Sept 2011

Roll-to-roll processing Oxford vacuum web coater Webspeed up to 5 ms -1 Web width 350 mm 4 4 4 21 st Sept 2011

The story so far……. Source and Drain (Metal) Possible interlayer L W Insulator (acrylic) Org. Semiconductor Possible surface modification Gate Substrate (e.g. PET) V S-D (V) -40 -30 -20 -10 0 0 (nA) -5 S-D I 0V -10V -20V -10 -30V -40V 5 5 21 st Sept 2011

Materials developments • Moved from glass to PEN substrates • Moved from Au to Al gate electrode • New masks: shorter S/D length, multiple transistors • Tried new semiconductor, DNTT Anticipated better stability Pentacenes Still high mobility • Tried insulator acrylate with higher S permittivity Thinner layer deposition S More polarizable DiNapthoThienoThiophene DNTT 6 6 21 st Sept 2011

Depositing the insulator • In-line process • High speed i. Evaporate monomer (liquid) ii. Condenses onto substrate (web) as a liquid (flat) iii. Polymerize (cure) in-situ 7 7 21 st Sept 2011

E-beam cure • FTIR indicates ‘full’ cure • IV curves of e-beam cured device • Poor saturation, greater hysteresis, poor stability V D (V) -40 -30 -20 -10 0 -4 100 0 10 960nm @ V D =-60V 10 -5 10 425 nm @V D =-40V -2 I on / I off = 1.3x10 3 1 -6 I D (µA) 10 I D (µA) D (A) V th = 10V (A) 0.1 -7 10 -4 I D I µ = 0.1cm 2 /Vs 0.01 -8 -10V 10 -20V -6 0.001 -30V -9 10 -40V -10 10 -60 -40 -20 0 20 V G (V) You can ‘solve’ these issues by annealing • Anneal at 150 C for 1 hour NB At a web speed of 50m/min, this annealing time requires a web path length of 3km! 8 8 21 st Sept 2011

Plasma cure • Cures in a single pass of the plasma as the polymer is deposited (although several passes of deposition are made for small-scale experiments) 100 4 100 5 -30V -30V- drak 10 I on / I off =3.2x10 3 I on / I off =1.1x10 3 3 4 10 ( I D ) 1/2 (µA 1/2 ) ( I D ) 1/2 (µA 1/2 ) I D (mA ) 1.0 I D (mA ) 3 1 2 0.1 2 0.1 0.01 1 1 0.01 0.001 0 0 -40 -20 0 20 -40 -20 0 20 V G (V) V G (V) E-beam-cured TRPGDA Plasma-cured TRPGDA 9 9 21 st Sept 2011

Device Lifetimes 10 1st scan (001) 10th scan 2 ) Intensity (a.u) 1/2 (µA) 1 ( µ A 1/2 D -1 I 10 ) D 1 ( I V =-50V d (002) -2 3 10 I /I off =2.1X10 on (003) (004) (005) 0 -3 10 -40 -20 0 20 5 10 15 20 25 30 θ 2 (degrees) V (V) G 0.0 -1.0 I D (µA) OFETs with plasma-cured dielectric show a reasonably -10V -2.0 -20V stable performance in air over -30V 10 cycles -40V -50V -3.0 -50 -40 -30 -20 -10 0 V (V) D 10 21 st Sept 2011

Shelf-life stability 10 -5 1st week 10 -6 I D (A) 10 -7 10 -8 15-weeks 10 -9 -60 -40 -20 0 20 (V) V 1 st Week 15 th Week G 1.5 4 2.0x10 3 1.8x10 2 1st week 1/2 I on / I off 1/2 (µA) 3 (µA) 1.0 V th (V) 10 -13 2 1/2 1/2 ) µ (cm 2 /Vs) 0.1 0.07 ) 0.5 D D 1 ( I ( I 15 weeks 0 0.0 -60 -40 -20 0 20 40 V (V) G 11 21 st Sept 2011

Interfacial modification • Self-assembled monolayers are required in printed organic transistors • Modify the insulator surface to become more hydrophobic • A hydrophobic (PS) layer gives improved pentacene morphology & devices with PS without PS without PS with PS Scale: 1µm = 0 10 20 30 Less effect is seen with fresh pentacene material 12 12 21 st Sept 2011

Surface modification Improved pentacene morphology gives better devices Greater mobility, lower off-current 13 13 21 st Sept 2011

Testing in Vacuum • See a lower off-current and higher mobility Device Performance (devices with PS layer characterised in vacuum) • I on / I off up to 10 7 , Mobility ≥ 0.4cm 2 /Vs • Very small operational degradation at moderate voltage 0 -12 Id(µA) -24 -36 Transfer and IV curves of pentacene on SB3 dielectric on PEN substrate • Investigate encapsulation methods 14 14 21 st Sept 2011

Device encapsulation • Well-established vacuum deposition methods for gas barrier layers • Used for food packaging • e.g. acrylate insulator/smoothing layer followed by Al or AlOx • Could be fully-integrated into the process Al, acrylate barrier layer Source and Drain (Au) L W PS interlayer DNTT or pentacene Insulator (acrylic) Al, acrylate barrier layer Gate (Al) Substrate (PEN) 15 15 21 st Sept 2011

Progress so far….. 1) Process parameters in R2R environment – building and testing transistors Shorter S/D length Plastic substrates Al gate electrode Improved curing method Surface modification layer Hysteresis measurements In-vacuum testing 16 16 21 st Sept 2011

Progress so far…… 2) Circuit design tailored for the properties achievable with this manufacturing route Transistor modelling underway based on device measurements 3) Materials (semiconductor and gate insulator layer) developed for this manufacturing route New SC synthesised, more under development Tried new insulator material 4) Patterning processes Favoured options for SC and insulator layers under development 5) Robustness of final devices Planning encapsulation experiments 17 17 21 st Sept 2011